Magnetoresistance and transistor-like behavior of a double quantum-dot via crossed Andreev reflections

The electric current and the magnetoresistance effect are studied in a double quantum-dot system, where one of the dots QD(a) is coupled to two ferromagnetic electrodes (F-1; F-2), while the second QD(b) is connected to a superconductor S. For energy scales within the superconductor gap, electric conduction is allowed by Andreev reflection processes. Due to the presence of two ferromagnetic leads, non-local crossed Andreev reflections are possible. We found that the magnetoresistance sign can be changed by tuning the external potential applied to the ferromagnets. In addition, it is possible to control the current of the first ferromagnet (F-1) through the potential applied to the second one (F-2). We have also included intradot interaction and gate voltages at each quantum dot and analyzed their influence through a mean field approximation. The interaction reduces the current amplitudes with respect to the non-interacting case, but the switching effect still remains as a manifestation of quantum coherence, in scales of the order of the superconductor coherence length. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4723000]

Universal zero-bias conductance for the single-electron transistor

The thermal dependence of the zero-bias conductance for the single electron transistor is the target of two independent renormalization-group approaches, both based on the spin-degenerate Anderson impurity model. The first approach, an analytical derivation, maps the Kondo-regime conductance onto the universal conductance function for the particle-hole symmetric model. Linear, the mapping is parametrized by the Kondo temperature and the charge in the Kondo cloud. The second approach, a numerical renormalization-group computation of the conductance as a function the temperature and applied gate voltages offers a comprehensive view of zero-bias charge transport through the device. The first approach is exact in the Kondo regime; the second, essentially exact throughout the parametric space of the model. For illustrative purposes, conductance curves resulting from the two approaches are compared.

A tunable triode-MOSFET transconductor and its application to g(m)-C filters

A linear, tunable CMOS transconductance stage is introduced. Drain voltage of the input transistor operating in triode region is settled by a regulation loop and a first-order linear relationship between g(m) and a de bias voltage is achieved. In addition to easy tuning, this technique offers circuit simplicity, wide dynamic range, high input and output impedances and low consumption. The transconductor is presented on both single-ended and fully-differential versions. A 3rd-order elliptical low-pass g(m)-C filter with a nominal roll-off frequency of 2MHz is used as one example for the many applications of the proposed transconductor. SPICE data describe circuits performances and filter tunabilily Passband is tuned at a rate of 2.36KHz/mV and good linearity is indicated by a 0.89% THD for an 800mV(p-p) balanced-driven input.

A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

A CMOS/SOI single-input PWM discriminator for low-voltage body-implanted applications

A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM) signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mum single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm(2). Measured resolution of encoding parameter a is better than 10% at 6 MHz and V-DD = 3.3 V. Idle-mode consumption is 340 LW. Pulses of frequencies up to 15 MHz and alpha = 10% can be discriminated for 2.3 V less than or equal to V-DD less than or equal to 3.3 V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to (gm)-C filters

A linearly tunable low-voltage CMOS transconductor featuring a new adaptative-bias mechanism that considerably improves the stability of the processed-signal common,mode voltage over the tuning range, critical for very-low voltage applications, is introduced. It embeds a feedback loop that holds input devices on triode region while boosting the output resistance. Analysis of the integrator frequency response gives an insight into the location of secondary poles and zeros as function of design parameters. A third-order low-pass Cauer filter employing the proposed transconductor was designed and integrated on a 0.8-mum n-well CMOS standard process. For a 1.8-V supply, filter characterization revealed f(p) = 0.93 MHz, f(s) = 1.82 MHz, A(min) = 44.08, dB, and A(max) = 0.64 dB at nominal tuning. Mined by a de voltage V-TUNE, the filter bandwidth was linearly adjusted at a rate of 11.48 kHz/mV over nearly one frequency decade. A maximum 13-mV deviation on the common-mode voltage at the filter output was measured over the interval 25 mV less than or equal to V-TUNE less than or equal to 200 mV. For V-out = 300 mV(pp) and V-TUNE = 100 mV, THD was -55.4 dB. Noise spectral density was 0.84 muV/Hz(1/2) @1 kHz and S/N = 41 dB @ V-out = 300 mV(pp) and 1-MHz bandwidth. Idle power consumption was 1.73 mW @V-TUNE = 100 mV. A tradeoff between dynamic range, bandwidth, power consumption, and chip area has then been achieved.

On designing linearly-tunable ultra-low voltage CMOS gm-C filters

A linearly-tunable ULV transconductor featuring excellent stability of the processed signal common-mode voltage upon tuning, critical for very-low voltage applications, is presented. Its employment to the synthesis of CMOS gm-C high-frequency and voiceband filters is discussed. SPICE data describe the filter characteristics. For a 1.3 V-supply, their nominal passband frequencies are 1.0 MHz and 3.78 KHz, respectively, with tuning rates of 12.52 KHz/mV and 0.16 KHz/m V, input-referred noise spectral density of 1.3 μV/Hz1/2 and 5.0μV/Hz1/2 and standby consumption of 0.87 mW and 11.8 μW. Large-signal distortion given by THD = 1% corresponds to a differential output-swing of 360 mVpp and 480 mVpp, respectively. Common-mode voltage deviation is less than 4 mV over tuning interval.

A high speed 3.3V current mode CMOS comparators with 10-b resolution

This paper presents a high speed current mode CMOS comparator. The comparator was optimized for allows wide range input current 1mA, ±0.5uA resolution and has fast response. This circuit was implemented with 0.8μm CMOS n-well process with area of 120μm × 105μm and operates with 3.3V(±1.65V).

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift

A new topology for a LVLP variable-gain CMOS amplifier is presented. Input- and load-stage are built around triode-transconductors so that voltage-gain is fully defined by a linear relationship involving only device-geometries and biases. Excellent gain-accuracy, temperature-insensitivity; and wide range of programmability, are thus achieved. Moreover, adaptative biasing improves the common-mode voltage stability upon gain-adjusting. As an example, a 0-40dB programmablegain audio-amplifier is designed. Its performance is supported by a range of simulations. For VDD=1.8V and 20dB-nominal gain, one has Av=19.97dB, f3db=770KHz and quiescent dissipation of 378μW. Over temperatures from -25°C to 125°C, the 0. ldB-bandwidth is 52KHz. Dynamic-range is optimized to 57.2dB and 42.6dB for gains of 20dB and 40dB, respectively. THD figures correspond to -60.6dB@Vout= 1Vpp and -79.7dB@Vout= 0.5 Vpp. A nearly constant bandwidth for different gains is also attained.

CMOS-based active pixel for low-light-level detection: Analysis and measurements

An analysis of the active pixel sensor (APS), considering the doping profiles of the photodiode in an APS fabricated in a 0.18 μm standard CMOS technology, is presented. A simple and accurate model for the junction capacitance of the photodiode is proposed. An analytic expression for the output voltage of the APS obtained with this capacitance model is in good agreement with measurements and is more accurate than the models used previously. A different mode of operation for the APS based on the dc level of the output is suggested. This new mode has better low-light-level sensitivity than the conventional APS operating mode, and it has a slower temporal response to the change of the incident light power. At 1μW/cm2 and lower levels of light, the measured signal-to-noise ratio (SNR) of this new mode is more than 10 dB higher than the SNR of previously reported APS circuits. Also, with an output SNR of about 10 dB, the proposed dc level is capable of detecting light powers as low as 20 nW/cm2, which is about 30 times lower than the light power detected in recent reports by other groups. © 2007 IEEE.

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35νm and was characterized for sensitivity and color response. The pixel is composed of an n+/psub photodiode, a comparator and a D flip-flop having 16% fill-factor and 30νmx26νm dimensions. The multisampling architecture requires only a 1 bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The advantage is that the number of transistors in the pixel is low, saving area and providing higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operation in video mode with 10 bits. Also, we present analysis for the impact of comparator offset voltage in the fixed pattern noise. Copyright 2007 ACM.

Design of a CMOS voltage reference using current-model approach

A voltage reference with low sensibility to temperature and power-supply that can generate flexible reference values (from milivolts to several volts) is proposed. Designed for AMS 0.35μm CMOS process, the circuit provides a stable output voltage working in the temperature range of -40-150°C. The proposed reference provides a nominal output voltage of 1.358V with a power-supply of 3.3V. © 2011 IEEE.

Sintetizador analógico de sinais ortogonais: projeto e construção usando tecnologia CMOS

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)