Mnltiloop Controller and Reference Generator for a Dynamic Voltage Restorer Implementation

This paper deals with the design and analysis of a Dynamic Voltage Restorer output voltage control. Such control is based on a multiloop strategy, with an inner current PID regulator and an outer P+Resonant voltage controller. The inner regulator is applied on the output inductor current. It will be also demonstrated how the load current behavior may influence in the DVR output voltage, which. justifies the need for the resonant controller. Additionally, it will be discussed the application of a modified algorithm for the identification of the DVR voltage references, which is based on a previously presented positive sequence detector. Since the studied three-phase DVR is assumed to be based on three identical H-bridge converters, all the analysis and design procedures were realized by means of single-phase equivalent circuits. The discussions and conclusions are supported by theoretical calculations, nonlinear simulations and some experimental results.

Towards an intelligent graphical interface for linear programming modelling

The increase of computing power of the microcomputers has stimulated the building of direct manipulation interfaces that allow graphical representation of Linear Programming (LP) models. This work discusses the components of such a graphical interface as the basis for a system to assist users in the process of formulating LP problems. In essence, this work proposes a methodology which considers the modelling task as divided into three stages which are specification of the Data Model, the Conceptual Model and the LP Model. The necessity for using Artificial Intelligence techniques in the problem conceptualisation and to help the model formulation task is illustrated.

Optimality conditions for pareto nonsmooth nonconvex programming in banach spaces

In this paper, we consider a vector optimization problem where all functions involved are defined on Banach spaces. We obtain necessary and sufficient criteria for optimality in the form of Karush-Kuhn-Tucker conditions. We also introduce a nonsmooth dual problem and provide duality theorems.

New approach of induction machine drive using an adaptive digital PID controller with gain planning based on artificial neural networks

The present work introduces a new strategy of induction machines speed adjustment using an adaptive PID (Proportional Integral Derivative) digital controller with gain planning based on the artificial neural networks. This digital controller uses an auxiliary variable to determine the ideal induction machine operating conditions and to establish the closed loop gain of the system. The auxiliary variable value can be estimated from the information stored in a general-purpose artificial neural network based on CMAC (Cerebellar Model Articulation Controller).

Design of microirrigation systems in sloping lands using linear programming

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift

A new topology for a LVLP variable-gain CMOS amplifier is presented. Input- and load-stage are built around triode-transconductors so that voltage-gain is fully defined by a linear relationship involving only device-geometries and biases. Excellent gain-accuracy, temperature-insensitivity; and wide range of programmability, are thus achieved. Moreover, adaptative biasing improves the common-mode voltage stability upon gain-adjusting. As an example, a 0-40dB programmablegain audio-amplifier is designed. Its performance is supported by a range of simulations. For VDD=1.8V and 20dB-nominal gain, one has Av=19.97dB, f3db=770KHz and quiescent dissipation of 378μW. Over temperatures from -25°C to 125°C, the 0. ldB-bandwidth is 52KHz. Dynamic-range is optimized to 57.2dB and 42.6dB for gains of 20dB and 40dB, respectively. THD figures correspond to -60.6dB@Vout= 1Vpp and -79.7dB@Vout= 0.5 Vpp. A nearly constant bandwidth for different gains is also attained.

VAr planning using genetic algorithm and linear programming

A combined methodology consisting of successive linear programming (SLP) and a simple genetic algorithm (SGA) solves the reactive planning problem. The problem is divided into operating and planning subproblems; the operating subproblem, which is a nonlinear, ill-conditioned and nonconvex problem, consists of determining the voltage control and the adjustment of reactive sources. The planning subproblem consists of obtaining the optimal reactive source expansion considering operational, economical and physical characteristics of the system. SLP solves the optimal reactive dispatch problem related to real variables, while SGA is used to determine the necessary adjustments of both the binary and discrete variables existing in the modelling problem. Once the set of candidate busbars has been defined, the program implemented gives the location and size of the reactive sources needed, if any, to maintain the operating and security constraints.

On the solution of mathematical programming problems with equilibrium constraints

Mathematical programming problems with equilibrium constraints (MPEC) are nonlinear programming problems where the constraints have a form that is analogous to first-order optimality conditions of constrained optimization. We prove that, under reasonable sufficient conditions, stationary points of the sum of squares of the constraints are feasible points of the MPEC. In usual formulations of MPEC all the feasible points are nonregular in the sense that they do not satisfy the Mangasarian-Fromovitz constraint qualification of nonlinear programming. Therefore, all the feasible points satisfy the classical Fritz-John necessary optimality conditions. In principle, this can cause serious difficulties for nonlinear programming algorithms applied to MPEC. However, we show that most feasible points do not satisfy a recently introduced stronger optimality condition for nonlinear programming. This is the reason why, in general, nonlinear programming algorithms are successful when applied to MPEC.

A low-voltage programmable-gain current-mode amplifier

A CMOS low-voltage, wide-band continuous-time current amplifier is presented. Based on an open-loop topology, the circuit is composed by transresistance and transconductance stages built around triode-operating transistors. In addition to an extended dynamic range, the amplifier gain can be programmed within good accuracy by the rapport between the aspect-ratio of such transistors and tuning biases Vxand Vy. A balanced current-amplifier according to a single I. IV-supply and a 0.35μm fabrication process is designed. Simulated results from PSPiCE and Bsm3v3 models indicate a programmable gain within the range 20-34dB and a minimum break-frequency of IMHz @CL=IpF. For a 200 μApp-level, THD is 0.8% and 0.9% at IKHz and 100KHz, respectively. Input noise is 405pA√Hz @20dB-gain, which gives a SNR of 66dB @1MHz-bandwidth. Maximum quiescent power consumption is 56μ W. © 2002 IEEE.

A novel programmable PFC based hybrid rectifier for ultra clean power application

A novel hybrid high power rectifier capable to achieve unity power factor is proposed in this paper. Single-phase SEPIC rectifiers are associated in parallel with each leg of three-phase 6-pulse diode rectifier resulting in a programmable input current waveform structure. In this paper it is described the principles of operation of the proposed converter with detailed simulation and experimental results. For a total harmonic distortion of the input line current (THDI) less than 2% the rated power of the SEPIC rectifiers is 33%. Therefore, power rating of the SEPIC parallel converters is a fraction of the output power, on the range of 20% to 33% of the nominal output power, making the proposed solution economically viable for high power installations, with fast pay back of the investment. Moreover, retrofits to existing installations are also possible with this proposed topology, since the parallel path can be easily controlled by integration with the already existing de-link. Experimental results are presented for a 3 kW implemented prototype, in order to verify the developed analysis.

Dynamic programming approach for road centerline extraction from digital images

This paper presents a dynamic programming approach for semi-automated road extraction from medium-and high-resolution images. This method is a modified version of a pre-existing dynamic programming method for road extraction from low-resolution images. The basic assumption of this pre-existing method is that roads manifest as lines in low-resolution images (pixel footprint> 2 m) and as such can be modeled and extracted as linear features. On the other hand, roads manifest as ribbon features in medium- and high-resolution images (pixel footprint ≤ 2 m) and, as a result, the focus of road extraction becomes the road centerlines. The original method can not accurately extract road centerlines from medium- and high- resolution images. In view of this, we propose a modification of the merit function of the original approach, which is carried out by a constraint function embedding road edge properties. Experimental results demonstrated the modified algorithm's potential in extracting road centerlines from medium- and high-resolution images.

Open and standardized tools for smart transducer networking

IEEE 1451 Standard is intended to address the smart transducer interfacing problematic in network environments. Usually, proprietary hardware and software is a very efficient solution to in planent the IEEE 1451 normative, although can be expensive and inflexible. In contrast, the use of open and standardized tools for implementing the IEEE 1451 normative is proposed in this paper. Tools such as Java and Phyton programming languages, Linux, programmable logic technology, Personal Computer resources and Ethernet architecture were integrated in order to constructa network node based on the IEEE 1451 standards. The node can be applied in systems based on the client-server communication model The evaluation of the employed tools and expermental results are presented. © 2005 IEEE.

Conception of wheeled mobile robots with reconfigurable control using integrate prototyping

With the fast innovation of the hardware and software technologies using rapid prototyping devices, with application in the robotics and automation, more and more it becomes necessary the development of applications based on methodologies that facilitate future modifications, updates and enhancements in the original projected system. This paper presents a conception of mobile robots using rapid prototyping, distributing the several control actions in growing levels of complexity and using resources of reconfigurable computing proposal oriented to embed systems implementation. Software and the hardware are structuralized in independents blocks, with connection through common bus. The study and applications of new structures control that permits good performance in relation to the parameter variations. This kind of controller can be tested on different platform representing the wheeled mobile robots using reprogrammable logic components (FPGA). © 2006 IEEE.

Proposal of architecture for launcher systems of unguided sounding rockets

This work presents a proposal of systemic architecture, to make automatic actions in the positioning of launch rail of unguided sounding rockets, which are based on a supervision system, a programmable logical controller, a sensory and actuators, available in Brazilian national market. Copyright © 2006 Society of Automotive Engineers, Inc.