Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n +/- 1 (n = odd) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation.

Effect of iodine concentration on the photovoltaic properties of dye sensitized solar cells for various I-2/LiI ratios

In the present study, the effect of iodine concentration on the photovoltaic properties of dye sensitized solar cells (DSSC) based on TiO2 nanoparticles for three different ratios of lithium iodide (LiI) and iodine (I-2) has been investigated. The electron transport properties and interfacial recombination kinetics have been evaluated by electrochemical impedance spectroscopy (EIS). It is found that increasing the concentration of lithium iodide for all ratios of iodine and lithium iodide decreases the open-circuit voltage (V-oc) whereas short circuit current density (J(sc)) and fill factor (FF) shows improvement. The reduction in V-oc and increment in J(sc) is ascribed to the higher concentration of absorptive Li+ cations which shifts the conduction band edge of TiO2 positively. The increase in FF is due to the reduction in electron transport resistance (R-omega) of the cell. In addition for all the ratios of LiI/I-2 increasing the concentration of I-2 decreases the V-oc which is attributed to the increased recombination with tri-iodide ions (I-3(-)) as verified from the low recombination resistance (R-k) and electron lifetime (tau) values obtained by EIS analysis. (C) 2012 Elsevier Ltd. All rights reserved.

Correlation between corona current and radio interference due to high voltage insulator string

The Radio Interference (RI) from electric power transmission line hardware, if not controlled, poses serious electromagnetic interference to system in the vicinity. The present work mainly concerns with the RI from the insulator string along with the associated line hardware. The laboratory testing for the RI levels are carried out through the measurement of the conducted radio interference levels. However such measurements do not really locate the coronating point, as well as, the mode of corona. At the same time experience shows that it is rather difficult to locate the coronating points by mere inspection. After a thorough look into the intricacies of the problem, it is ascertained that the measurement of associated ground end currents could give a better picture of the prevailing corona modes and their intensities. A study on the same is attempted in the present work. Various intricacies of the problem,features of ground end current pulses and its correlation with RI are dealt with. Owing to the complexity of such experimental investigations, the study made is not fully complete nevertheless it seems to be first of its kind.

Reactive power and voltage control in grid connected wind farms

Wind power, as an alternative to fossil fuels, is plentiful, renewable, widely distributed, clean, produces no greenhouse gas emissions during operation, and uses little land. In operation, the overall cost per unit of energy produced is similar to the cost for new coal and natural gas installations. However, the stochastic behaviour of wind speeds leads to significant disharmony between wind energy production and electricity demand. Wind generation suffers from an intermittent characteristics due to the own diurnal and seasonal patterns of the wind behaviour. Both reactive power and voltage control are important under varying operating conditions of wind farm. To optimize reactive power flow and to keep voltages in limit, an optimization method is proposed in this paper. The objective proposed is minimization of the voltage deviations of the load buses (Vdesired). The approach considers the reactive power limits of wind generators and co-ordinates the transformer taps. This algorithm has been tested under practically varying conditions simulated on a test system. The results are obtained on a system of 50-bus real life equivalent power network. The result shows the efficiency of the proposed method.

Performance improvement of short-length regular low-density parity-check codes with low-complexity post-processing

It is well known that extremely long low-density parity-check (LDPC) codes perform exceptionally well for error correction applications, short-length codes are preferable in practical applications. However, short-length LDPC codes suffer from performance degradation owing to graph-based impairments such as short cycles, trapping sets and stopping sets and so on in the bipartite graph of the LDPC matrix. In particular, performance degradation at moderate to high E-b/N-0 is caused by the oscillations in bit node a posteriori probabilities induced by short cycles and trapping sets in bipartite graphs. In this study, a computationally efficient algorithm is proposed to improve the performance of short-length LDPC codes at moderate to high E-b/N-0. This algorithm makes use of the information generated by the belief propagation (BP) algorithm in previous iterations before a decoding failure occurs. Using this information, a reliability-based estimation is performed on each bit node to supplement the BP algorithm. The proposed algorithm gives an appreciable coding gain as compared with BP decoding for LDPC codes of a code rate equal to or less than 1/2 rate coding. The coding gains are modest to significant in the case of optimised (for bipartite graph conditioning) regular LDPC codes, whereas the coding gains are huge in the case of unoptimised codes. Hence, this algorithm is useful for relaxing some stringent constraints on the graphical structure of the LDPC code and for developing hardware-friendly designs.

Multilevel octadecagonal space vector generation for induction motor drives by cascading asymmetric three level inverters

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18 sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three level inverters. By proper selection of DC link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector based PWM techniques are the complete elimination of fifth, seventh, eleventh and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Matlab simulation results and experimental results have been presented in this paper to validate the proposed concept.

A nine-level inverter topology for medium-voltage induction motor drive with open-end stator winding

A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected H-bridges. The H-bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five-or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the H-bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region.

Common-mode voltage eliminated three-level inverter using a three-level flying-capacitor inverter and cascaded H-bridge

This paper proposes a new 3 level common mode voltage eliminated inverter using an inverter structure formed by cascading a H-Bridge with a three-level flying capacitor inverter. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-Bridge fails, the system can still be operated as a normal 3 level inverter mode at full power. This inverter has many advantages like use of single DC-supply, making it possible for a back to back grid-tied converter application, improved reliability etc.

Analysis of voltage stability in multi-infeed HVDC systems with STATCOM

This paper presents the modelling and analysis of voltage stability at AC commutation bus in LCC (Line commutated converters) based multi-infeed HVDC system. The paper also presents the analysis of effects of various operating control modes in HVDC as well as location of disturbance on the voltage stability of the system under study. A new method of modelling the LCC converters as time varying admittance at the AC commutation bus is also presented in this paper. In this paper, the modelling of STATCOM for provision of dynamic voltage support at one of the AC buses of the HVDC system is presented. The reactive power injected by STATCOM is controlled by regulating the voltage of the AC bus to which STATCOM is connected. The case study also discusses the effects of various possible combinations of location of STATCOM and disturbance considered, on the voltage stability of the multi-infeed HVDC system.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Space vector-based analysis of overmodulation in triangle-comparison based PWM for voltage source inverter

The equivalence of triangle-comparison-based pulse width modulation (TCPWM) and space vector based PWM (SVPWM) during linear modulation is well-known. This paper analyses triangle-comparison based PWM techniques (TCPWM) such as sine-triangle PWM (SPWM) and common-mode voltage injection PWM during overmodulation from a space vector point of view. The average voltage vector produced by TCPWM during overmodulation is studied in the stationary (a-b) reference frame. This is compared and contrasted with the average voltage vector corresponding to the well-known standard two-zone algorithm for space vector modulated inverters. It is shown that the two-zone overmodulation algorithm itself can be derived from the variation of average voltage vector with TCPWM. The average voltage vector is further studied in a synchronously revolving (d-q) reference frame. The RMS value of low-order voltage ripple can be estimated, and can be used to compare harmonic distortion due to different PWM methods during overmodulation. The measured values of the total harmonic distortion (THD) in the line currents are presented at various fundamental frequencies. The relative values of measured current THD pertaining to different PWM methods tally with those of analytically evaluated RMS voltage ripple.

A naturally occurring amino acid substitution in the voltage-dependent sodium channel selectivity filter affects channel gating

The pore of sodium channels contains a selectivity filter made of 4 amino acids, D/E/K/A. In voltage sensitive sodium channel (Nav) channels from jellyfish to human the fourth amino acid is Ala. This Ala, when mutated to Asp, promotes slow inactivation. In some Nav channels of pufferfishes, the Ala is replaced with Gly. We studied the biophysical properties of an Ala-to-Gly substitution (A1529G) in rat Nav1.4 channel expressed in Xenopus oocytes alone or with a beta 1 subunit. The Ala-to-Gly substitution does not affect monovalent cation selectivity and positively shifts the voltage-dependent inactivation curve, although co-expression with a beta 1 subunit eliminates the difference between A1529G and WT. There is almost no difference in channel fast inactivation, but the beta 1 subunit accelerates WT current inactivation significantly more than it does the A1529G channels. The Ala-to-Gly substitution mainly influences the rate of recovery from slow inactivation. Again, the beta 1 subunit is less effective on speeding recovery of A1529G than the WT. We searched Nav channels in numerous databases and noted at least four other independent Ala-to-Gly substitutions in Nav channels in teleost fishes. Thus, the Ala-to-Gly substitution occurs more frequently than previously realized, possibly under selection for alterations of channel gating.

Wide Voltage Input Receiver with Hysteresis Characteristic to Reduce Input Signal Noise Effect

In this paper, an input receiver with a hysteresis characteristic that can work at voltage levels between 0.9 V and 5 V is proposed. The input receiver can be used as a wide voltage range Schmitt trigger also. At the same time, reliable circuit operation is ensured. According to the research findings, this is the first time a wide voltage range Schmitt trigger is being reported. The proposed circuit is compared with previously reported input receivers, and it is shown that the circuit has better noise immunity. The proposed input receiver ends the need for a separate Schmitt trigger and input buffer. The frequency of operation is also higher than that of the previously reported receiver. The circuit is simulated using HSPICE at 035-mu m standard thin oxide technology. Monte Carlo analysis is conducted at different process conditions, showing that the proposed circuit works well for different process conditions at different voltage levels of operation. A noise impulse of (V-CC/2) magnitude is added to the input voltage to show that the receiver receives the correct logic level even in the presence of noise. Here, V-CC is the fixed voltage supply of 3.3 V.