Reuseable Silicon IP Cores for Discrete Wavelet Transform Applications

Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms.

A split-combination approach to merging knowledge bases in possibilistic logic

In this paper, we propose an adaptive approach to merging possibilistic knowledge bases that deploys multiple operators instead of a single operator in the merging process. The merging approach consists of two steps: one is called the splitting step and the other is called the combination step. The splitting step splits each knowledge base into two subbases and then in the second step, different classes of subbases are combined using different operators. Our approach is applied to knowledge bases which are self-consistent and the result of merging is also a consistent knowledge base. Two operators are proposed based on two different splitting methods. Both operators result in a possibilistic knowledge base which contains more information than that obtained by the t-conorm (such as the maximum) based merging methods. In the flat case, one of the operators provides a good alternative to syntax-based merging operators in classical logic.

Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

Probabilistic nonlocal gate operation via imperfect entanglement

Nonlocal gate operation is based on sharing an ancillary pair of qubits in perfect entanglement. When the ancillary pair is partially entangled, the efficiency of gate operation drops. Using general transformations, we devise probabilistic nonlocal gates, which perform the nonlocal operation conclusively when the ancillary pair is only partially entangled. We show that a controlled purification protocol can be implemented by the probabilistic nonlocal operation.

A recursive rule base adjustment algorithm for a fuzzy logic controller

This paper introduces a recursive rule base adjustment to enhance the performance of fuzzy logic controllers. Here the fuzzy controller is constructed on the basis of a decision table (DT), relying on membership functions and fuzzy rules that incorporate heuristic knowledge and operator experience. If the controller performance is not satisfactory, it has previously been suggested that the rule base be altered by combined tuning of membership functions and controller scaling factors. The alternative approach proposed here entails alteration of the fuzzy rule base. The recursive rule base adjustment algorithm proposed in this paper has the benefit that it is computationally more efficient for the generation of a DT, and advantage for online realization. Simulation results are presented to support this thesis. (c) 2005 Elsevier B.V. All rights reserved.