Compiler Assisted Leakage Energy Optimization for Clustered VLIW Architectures

Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. Relatively simpler issue logic and the presence of a large number of function units in the VLIW and the clustered VLIW architectures attribute a large fraction of this leakage energy consumption in the functional units. However, functional units are not fully utilized in the VLIW architectures because of the inherent variations in the ILP of the programs. This underutilization is even more pronounced in the context of clustered VLIW architectures because of the contentions for the limited number of slow intercluster communication channels which lead to many short idle cycles.In the past, some architectural schemes have been proposed to obtain leakage energy bene .ts by aggressively exploiting the idleness of functional units. However, presence of many short idle cycles cause frequent transitions from the active mode to the sleep mode and vice-versa and adversely a ffects the energy benefits of a purely hardware based scheme. In this paper, we propose and evaluate a compiler instruction scheduling algorithm that assist such a hardware based scheme in the context of VLIW and clustered VLIW architectures. The proposed scheme exploits the scheduling slacks of instructions to orchestrate the functional unit mapping with the objective of reducing the number of transitions in functional units thereby keeping them off for a longer duration. The proposed compiler-assisted scheme obtains a further 12% reduction of energy consumption of functional units with negligible performance degradation over a hardware-only scheme for a VLIW architecture. The benefits are 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively. Our test bed uses the Trimaran compiler infrastructure.

Design and Optimization of Broadband Micromachined Antenna

Performance improvement of a micromachined patch antenna operating at 30 GHz with a capacitively coupled feed arrangement is presented here. Such antennas are useful for monolithic integration with active components. Specifically, micromachining can be employed to achieve a low dielectric constant region under the patch which causes (i) the suppression of surface waves and hence the increase in radiation efficiency and (ii) increase in the bandwidth. The performance of such a patch antenna can be significantly improved by selecting a coupled feed arrangement. We have optimized the dimensions and location of the capacitive feeding strip to get the maximum improvement in bandwidth. Since this is a totally planar arrangement, and does not involve any stacked structures, this antenna is easy to fabricate using standard microfabrication techniques. The antenna element thus designed has a -10 dB bandwidth of 1600 MHz

Simultaneous Geometry Optimization and Material Selection for Truss Structures

In this work, we explore simultaneous design and material selection by posing it as an optimization problem. The underlying principles for our approach are Ashby's material selection procedure and structural optimization. For the simplicity and ease of initial implementation of the general procedure, truss structures under static load are considered in this work in view of maximum stiffness, minimum weight/cost and safety against failure. Along the lines of Ashby's material indices, a new design index is derived for trusses. This helps in choosing the most suitable material for any design of a truss. Using this, both the design space and material database are searched simultaneously using optimization algorithms. The important feature of our approach is that the formulated optimization problem is continuous even though the material selection is an inherently discrete problem.

Topology Optimization of Micromachined Structures with Surface Micromachining Manufacturing Constraints

Topology optimization methods have been shown to have extensive application in the design of microsystems. However, their utility in practical situations is restricted to predominantly planar configurations due to the limitations of most microfabrication techniques in realizing structures with arbitrary topologies in the direction perpendicular to the substrate. This study addresses the problem of synthesizing optimal topologies in the out-of-plane direction while obeying the constraints imposed by surface micromachining. A new formulation that achieves this by defining a design space that implicitly obeys the manufacturing constraints with a continuous design parameterization is presented in this paper. This is in contrast to including manufacturing cost in the objective function or constraints. The resulting solutions of the new formulation obtained with gradient-based optimization directly provide the photolithographic mask layouts. Two examples that illustrate the approach for the case of stiff structures are included.

Topology Optimization of Electrostatically Actuated Micromechanical Structures with Accurate Electrostatic Modeling of the Interpolated Material Model

In this paper, we present a novel formulation for performing topology optimization of electrostatically actuated constrained elastic structures. We propose a new electrostatic-elastic formulation that uses the leaky capacitor model and material interpolation to define the material state at every point of a given design domain continuously between conductor and void states. The new formulation accurately captures the physical behavior when the material in between a conductor and a void is present during the iterative process of topology optimization. The method then uses the optimality criteria method to solve the optimization problem by iteratively pushing the state of the domain towards that of a conductor or a void in the appropriate regions. We present examples to illustrate the ability of the method in creating the stiffest structure under electrostatic force for different boundary conditions.

Swarm intelligence algorithms for integrated optimization of piezoelectric actuator and sensor placement and feedback gains

Swarm intelligence algorithms are applied for optimal control of flexible smart structures bonded with piezoelectric actuators and sensors. The optimal locations of actuators/sensors and feedback gain are obtained by maximizing the energy dissipated by the feedback control system. We provide a mathematical proof that this system is uncontrollable if the actuators and sensors are placed at the nodal points of the mode shapes. The optimal locations of actuators/sensors and feedback gain represent a constrained non-linear optimization problem. This problem is converted to an unconstrained optimization problem by using penalty functions. Two swarm intelligence algorithms, namely, Artificial bee colony (ABC) and glowworm swarm optimization (GSO) algorithms, are considered to obtain the optimal solution. In earlier published research, a cantilever beam with one and two collocated actuator(s)/sensor(s) was considered and the numerical results were obtained by using genetic algorithm and gradient based optimization methods. We consider the same problem and present the results obtained by using the swarm intelligence algorithms ABC and GSO. An extension of this cantilever beam problem with five collocated actuators/sensors is considered and the numerical results obtained by using the ABC and GSO algorithms are presented. The effect of increasing the number of design variables (locations of actuators and sensors and gain) on the optimization process is investigated. It is shown that the ABC and GSO algorithms are robust and are good choices for the optimization of smart structures.

Relay Precoder Optimization in MIMO-Relay Networks With Imperfect CSI

In this paper, we consider robust joint designs of relay precoder and destination receive filters in a nonregenerative multiple-input multiple-output (MIMO) relay network. The network consists of multiple source-destination node pairs assisted by a MIMO-relay node. The channel state information (CSI) available at the relay node is assumed to be imperfect. We consider robust designs for two models of CSI error. The first model is a stochastic error (SE) model, where the probability distribution of the CSI error is Gaussian. This model is applicable when the imperfect CSI is mainly due to errors in channel estimation. For this model, we propose robust minimum sum mean square error (SMSE), MSE-balancing, and relay transmit power minimizing precoder designs. The next model for the CSI error is a norm-bounded error (NBE) model, where the CSI error can be specified by an uncertainty set. This model is applicable when the CSI error is dominated by quantization errors. In this case, we adopt a worst-case design approach. For this model, we propose a robust precoder design that minimizes total relay transmit power under constraints on MSEs at the destination nodes. We show that the proposed robust design problems can be reformulated as convex optimization problems that can be solved efficiently using interior-point methods. We demonstrate the robust performance of the proposed design through simulations.

Underlap Optimization in HFinFET in Presence of Interface Traps

In this work, using 3-D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the ON-OFF ratio as well as the subthreshold characteristics in an ultrashort channel n-type device without significantON performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be promising when compared against ITRS 2009 performance projections, as well as published state of the art planar and nonplanar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques.