983 resultados para Modular coordination (Architecture)
Resumo:
REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.
Resumo:
Two IS- and 16-residue peptides containing a-aminoisobutyric acid (Aib) have been synthesized, as part of a strategy to construct stereochemically rigid peptide helices, in a modular approach to design of protein mimics. The peptides Boc-(Val-Ala-Leu-Aib),-OMe ( I ) and Boc-Val-Ala-Leu-Aib-Val-Ala-Leu-(Val-Ala-Leu-Aib()11z)- OhaMvee been crystallized.Both crystals are stable only in the presence of mother liquor or water. The crystal data are as follows. I: C78H140N16019~2H20,P2,, a = 16.391 (3) A, b = 16.860 (3) A, c = 18.428 (3) A, p = 103.02 (I)O, Z = 2, R = 9.6% for 3445 data with lFol >30(F), resolution 0.93 A. 11: C7,Hl,,N,S018.7.5H,0, C2221, a = 18.348 ( 5 ) A, b = 47.382 (1 1) A, c = 24.157 ( 5 ) A, Z =8, R = l0,6%, for 3147 data with lFol > 3a(F), resolution 1.00 A. The 15-residue peptide (11) is entirely a helical, while the 16-residue peptide ( I ) has a short segment of 310 helix at the N terminus. The packing of the helices in the crystals is rather incfficicnt with no particular attractions between Leu-Leu side chains, or any other pair. Both crystals have fairly large voids, which are filled with water molecules in a disordered fashion. Water molecule sites near the polar head-to-tail regions are well detcrmined, those closer to the hydrophobic side chains less so and a number of possible water sites in the remaining "empty" space are not determined. No interdigitation of Leu side chains is observed in the crystal as is hypothesized in the "leucine zipper" class of DNA binding proteins.
Resumo:
Two seven-residue helical segments, Val-Ala-Leu-Aib-Val-Ala-Leu, were linked synthetically with an epsilon-aminocaproic acid (Acp) linker with the intention of making a stable antiparallel helix-helix motif. The crystal structure of the linked peptide Boc-Val-Ala-Leu-Aib-Val-Ala-Leu-Acp-Val-Ala-Leu-Aib-Val-Ala-Leu-OMe (1) shows the two helices displaced laterally from each other by the linker, but the linker has not folded the molecule into a close-packed antiparallel conformation. Two strong intermolecular NH...O = C hydrogen bonds are formed between the top of the lower helix of one molecule and the bottom of the upper helix in a laterally adjacent molecule to give the appearance of an extended single helix. The composite peptide with Boc and OMe end groups, C76H137N15O18.H2O, crystallize in space group P2(1) with a = 8.802 (1) angstrom, b = 20.409 (4) angstrom, c = 26.315 (3) angstrom, and beta = 90.72 (1)degrees; overall agreement R = 7.86% for 5030 observed reflections (\F(o)\ > 3-sigma(F)); resolution = 0.93 angstrom. Limited evidence for a more compact conformation in solution consistent with an antiparallel helix arrangement is obtained by comparison of the HPLC retention times and CD spectra of peptide 1 with well-characterized continuous helices of similar length and sequence.
Resumo:
Nonconventional heptacoordination in combination with efficient magnetic exchange coupling is shown to yield a 1-D heteronuclear {(FeNbIV)-Nb-II} compound with remarkable magnetic features when compared to other Fe(II)-based single chain magnets (SCM). Cyano-bridged heterometallic {3d-4d} and {3d-5d} chains are formed upon assembling Fe(II) bearing a pentadentate macrocycle as the blocking ligand with octacyano metallates, [M(CN)(8)](4-) (M = Nb-IV, Mo-IV, W-IV.) X-ray diffraction (single-crystal and powder) measurements reveal that the [{(H2O)Fe(L-1)}{M(CN)(8)}{Fe(L-1)}](infinity) architectures consist of isomorphous 1-D polymeric structures based on the alternation of {Fe(L-1)}(2+) and {M(CN)(8)}(4-) units (L-1 stands for the pentadentate macrocycle). Analysis of the magnetic susceptibility behavior revealed cyano-bridged {Fe-Nb} exchange interaction to be antiferromagnetic with J = -20 cm(-1) deduced from fitting an Ising model taking into account the noncollinear spin arrangement. For this ferrimagnetic chain a slow relaxation of its magnetization is observed at low temperature revealing a SCM behavior with Delta/k(B) = 74 K and tau(0) = 4.6 x 10(-11) s. The M versus H behavior exhibits a hysteresis loop with a coercive field of 4 kOe at 1 K and reveals at 380 mK magnetic avalanche processes, i.e., abrupt reversals in magnetization as H is varied. The origin of these characteristics is attributed to the combination of efficient {Fe-Nb} exchange interaction and significant anisotropy of the {Fe(L-1)) unit. High field EPR and magnetization experiments have revealed for the parent compound [Fe(L-1)(H2O)(2)]Cl-2 a negative zero field splitting parameter of D approximate to -17 cm(-1). The crystal structure, magnetic behavior, and Mossbauer data for [Fe(L-1)(H2O)(2)]Cl-2 are also reported.
Resumo:
Nonconventional heptacoordination in combination with efficient magnetic exchange coupling is shown to yield a 1-D heteronuclear {(FeNbIV)-Nb-II} compound with remarkable magnetic features when compared to other Fe(II)-based single chain magnets (SCM). Cyano-bridged heterometallic {3d-4d} and {3d-5d} chains are formed upon assembling Fe(II) bearing a pentadentate macrocycle as the blocking ligand with octacyano metallates, [M(CN)(8)](4-) (M = Nb-IV, Mo-IV, W-IV.) X-ray diffraction (single-crystal and powder) measurements reveal that the [{(H2O)Fe(L-1)}{M(CN)(8)}{Fe(L-1)}](infinity) architectures consist of isomorphous 1-D polymeric structures based on the alternation of {Fe(L-1)}(2+) and {M(CN)(8)}(4-) units (L-1 stands for the pentadentate macrocycle). Analysis of the magnetic susceptibility behavior revealed cyano-bridged {Fe-Nb} exchange interaction to be antiferromagnetic with J = -20 cm(-1) deduced from fitting an Ising model taking into account the noncollinear spin arrangement. For this ferrimagnetic chain a slow relaxation of its magnetization is observed at low temperature revealing a SCM behavior with Delta/k(B) = 74 K and tau(0) = 4.6 x 10(-11) s. The M versus H behavior exhibits a hysteresis loop with a coercive field of 4 kOe at 1 K and reveals at 380 mK magnetic avalanche processes, i.e., abrupt reversals in magnetization as H is varied. The origin of these characteristics is attributed to the combination of efficient {Fe-Nb} exchange interaction and significant anisotropy of the {Fe(L-1)) unit. High field EPR and magnetization experiments have revealed for the parent compound [Fe(L-1)(H2O)(2)]Cl-2 a negative zero field splitting parameter of D approximate to -17 cm(-1). The crystal structure, magnetic behavior, and Mossbauer data for [Fe(L-1)(H2O)(2)]Cl-2 are also reported.
Resumo:
This paper aims at evaluating the methods of multiclass support vector machines (SVMs) for effective use in distance relay coordination. Also, it describes a strategy of supportive systems to aid the conventional protection philosophy in combating situations where protection systems have maloperated and/or information is missing and provide selective and secure coordinations. SVMs have considerable potential as zone classifiers of distance relay coordination. This typically requires a multiclass SVM classifier to effectively analyze/build the underlying concept between reach of different zones and the apparent impedance trajectory during fault. Several methods have been proposed for multiclass classification where typically several binary SVM classifiers are combined together. Some authors have extended binary SVM classification to one-step single optimization operation considering all classes at once. In this paper, one-step multiclass classification, one-against-all, and one-against-one multiclass methods are compared for their performance with respect to accuracy, number of iterations, number of support vectors, training, and testing time. The performance analysis of these three methods is presented on three data sets belonging to training and testing patterns of three supportive systems for a region and part of a network, which is an equivalent 526-bus system of the practical Indian Western grid.
Resumo:
H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.
Resumo:
The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.
Resumo:
Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.
Resumo:
In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.