COMPARISON OF PARTIAL SHADING LOSSES IN FREE FIELD PV-PLANTS WITH DIFFERENT ARRAY CONFIGURATIONS

A common problem when planning large free field PV-plants is optimizing the ground occupation ratio while maintaining low shading losses. Due to the complexity of this task, several PV-plants have been built using various configurations. In order to compare the shading losses of different PV technologies and array designs, empirical performance data of five free field PV-plants operating in Germany was analyzed. The data collected comprised 140 winter days from October 2011 until March 2012. The relative shading losses were estimated by comparing the energy output of selected arrays in the front rows (shading-free) against that of shaded arrays in the back rows of the same plant. The results showed that landscape mounting with mc-Si PV-modules yielded significantly better results than portrait one. With CIGS modules, making cross-table strings using the lower modules was not beneficial as expected and had more losses than a one-string-per-table layout. Parallel substrings with CdTe showed relatively low losses. Among the two CdTe products analyzed, none showed a significantly better performance.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

A novel system for large-scale gene expression analysis: bacterial colonies array

In the present work, we report the use of bacterial colonies to optimize macroarray technique. The devised system is significantly cheaper than other methods available to detect large-scale differential gene expression. Recombinant Escherichia coli clones containing plasmid-encoded copies of 4,608 individual expressed sequence tag (ESTs) were robotically spotted onto nylon membranes that were incubated for 6 and 12 h to allow the bacteria to grow and, consequently, amplify the cloned ESTs. The membranes were then hybridized with a beta-lactamase gene specific probe from the recombinant plasmid and, subsequently, phosphorimaged to quantify the microbial cells. Variance analysis demonstrated that the spot hybridization signal intensity was similar for 3,954 ESTs (85.8%) after 6 h of bacterial growth. Membranes spotted with bacteria colonies grown for 12 h had 4,017 ESTs (87.2%) with comparable signal intensity but the signal to noise ratio was fivefold higher. Taken together, the results of this study indicate that it is possible to investigate large-scale gene expression using macroarrays based on bacterial colonies grown for 6 h onto membranes.

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing

Sensor array made with nanostructured films to detect a phenothiazine compound

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Fibroblast functionality on novel Ti-30Ta nanotube array

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)