La teneur du standard de fiabilité des moyens électroniques de signature

Les institutions juridiques ont été bâties autour des réalités connues depuis des millénaires, que nous appelons de nos jours des phénomènes du monde réel. Ces phénomènes retrouvent présentement un nouveau théâtre – le cyberespace, et les règles du droit font face au défi de s’approprier ce nouvel environnement. Entre autres, les technologies du cyberespace ont mis au monde divers moyens qui nous permettent de nous identifier et de manifester notre attitude envers les actes juridiques – des finalités qui ont été assurées de longue date par la signature manuscrite. Bien que ces nouveaux moyens aient mérité un nom similaire à leur contrepartie traditionnelle – l’appellation de signature électronique, ils restent des phénomènes dont la proximité avec la signature manuscrite est discutable. Force est de constater que le seul point commun entre les moyens classiques et électroniques de signer réside dans les fonctions qu’ils remplissent. C’est en se basant sur ces fonctions communes que le droit a adopté une attitude identique envers les moyens d’authentification traditionnels et électroniques et a accueilli ces derniers sous l’emprise de ses institutions. Cependant, ceci ne signifie pas que ces institutions se soient avérées appropriées et qu’elles ne demandent aucun ajustement. Un des buts de notre étude sera de mettre en relief les moyens d’adaptation qu’offre le droit pour réconcilier ces deux environnements. Ainsi, pour ajuster l’institution de la signature aux phénomènes électroniques, le droit s’est tourné vers le standard de fiabilité de la signature électronique. Le standard de fiabilité est un complément de l’institution juridique de signature qui ne se rapporte qu’à la signature électronique et dont cette étude démontrera les applications. Les composantes du standard de fiabilité qui occuperont un deuxième volet de notre étude représentent un ensemble de règles techniques liées à la signature électronique. Ainsi, comme le standard de fiabilité puise sa substance dans les propriétés de l’architecture du cyberespace, l’attitude du droit envers la signature électronique s’avère tributaire de la morphologie du cyberespace. Étant donné que les possibilités qui nous sont offertes par la technologie continue à déterminer la réglementation juridique, il est légitime de conclure que l’examen des tendances dans l’évolution du cyberespace nous fournira un point de vue prospectif sur l’évolution des règles du droit.

Une évaluation de la dimension de la lumière de boîtiers 0,018" provenant de quatre différents manufacturiers. Existe-t-il un standard dans l’industrie?

Introduction: The objective of this experimental research was to evaluate the slot’s vertical dimension and profile of four different 0.018″ self-ligating brackets and to identify the level of tolerance accepted by manufacturers during the fabrication process. It was then possible to calculate and compare the torque play of those brackets using the measured values and the nominal values. Material and Methods: Twenty-five 0.018″ self-ligating brackets of upper left central incisors from the following manufacturers, Speed® (Strite Industries, Cambridge, Ontario, Canada), InOvationR® (GAC, Bohemia, NY, USA), CarriereLX® (Ortho Organizers, Carlsbad, CA, USA) and SmartClip® (3M Unitek, Monrovia, CA, USA), were evaluated using electron microscopy with 150X images. The height of each bracket was measured at every 100 microns of depth from the lingual wall at five different levels. A Student T test was then used to compare our results with the manufacturer’s stated value of 0.018″. To determine if there was a significant difference between the four manufacturers, analysis of variance (ANOVA) was performed at the significance level of p<0.05. The torque play was then calculated using geometrical formulas. Results: On average, Speed brackets were oversized by 2.7%[MV 0.0185″ (SD:0.002)], InOvationR by 3.7% [MV 0.0187″ (SD:0.002)], CarriereLX by 3.2% [MV 0.0186″ (SD:0.002)] and SmartClipSL by 5.0% [MV 0.0189″ (SD:0.002)]. The height of all brackets was significantly higher than the nominal value of 0.018″ (p<0.001). The slot of SmartClip brackets was significantly larger than those of the other three manufacturers (p<0.001). None of the brackets studied had parallel gingival and occlusal walls; some were convergent and others divergent. These variations can induce a torque play up to 4.5 degrees with a 0.017″x0.025″ wire and 8.0 degrees with a 0.016″x0.022″ wire. Conclusion: All studied brackets were oversized. None of the brackets studied had parallel gingival and occlusal walls and there was no standard between manufacturers for the geometry of their slots. These variations can cause a slight increase of the torque play between the wire and the bracket compared with the nominal value.

Développement d'un nouveau critère pour déterminer les limites d'utilisation des détecteurs en dosimétrie non standard

Depuis quelques années, il y a un intérêt de la communauté en dosimétrie d'actualiser les protocoles de dosimétrie des faisceaux larges tels que le TG-51 (AAPM) et le TRS-398 (IAEA) aux champs non standard qui requièrent un facteur de correction additionnel. Or, ces facteurs de correction sont difficiles à déterminer précisément dans un temps acceptable. Pour les petits champs, ces facteurs augmentent rapidement avec la taille de champ tandis que pour les champs d'IMRT, les incertitudes de positionnement du détecteur rendent une correction cas par cas impraticable. Dans cette étude, un critère théorique basé sur la fonction de réponse dosimétrique des détecteurs est développé pour déterminer dans quelles situations les dosimètres peuvent être utilisés sans correction. Les réponses de quatre chambres à ionisation, d'une chambre liquide, d'un détecteur au diamant, d'une diode, d'un détecteur à l'alanine et d'un détecteur à scintillation sont caractérisées à 6 MV et 25 MV. Plusieurs stratégies sont également suggérées pour diminuer/éliminer les facteurs de correction telles que de rapporter la dose absorbée à un volume et de modifier les matériaux non sensibles du détecteur pour pallier l'effet de densité massique. Une nouvelle méthode de compensation de la densité basée sur une fonction de perturbation est présentée. Finalement, les résultats démontrent que le détecteur à scintillation peut mesurer les champs non standard utilisés en clinique avec une correction inférieure à 1%.

A Novel Method for the 3-D Reconstruction of Scoliotic Ribs From Frontal and Lateral Radiographs

Among the external manifestations of scoliosis, the rib hump, which is associated with the ribs' deformities and rotations, constitutes the most disturbing aspect of the scoliotic deformity for patients. A personalized 3-D model of the rib cage is important for a better evaluation of the deformity, and hence, a better treatment planning. A novel method for the 3-D reconstruction of the rib cage, based only on two standard radiographs, is proposed in this paper. For each rib, two points are extrapolated from the reconstructed spine, and three points are reconstructed by stereo radiography. The reconstruction is then refined using a surface approximation. The method was evaluated using clinical data of 13 patients with scoliosis. A comparison was conducted between the reconstructions obtained with the proposed method and those obtained by using a previous reconstruction method based on two frontal radiographs. A first comparison criterion was the distances between the reconstructed ribs and the surface topography of the trunk, considered as the reference modality. The correlation between ribs axial rotation and back surface rotation was also evaluated. The proposed method successfully reconstructed the ribs of the 6th-12th thoracic levels. The evaluation results showed that the 3-D configuration of the new rib reconstructions is more consistent with the surface topography and provides more accurate measurements of ribs axial rotation.

Logique et Sémantique : Critique d’une interprétation non‐standard de la logique déontique

Ce texte porte sur l’analyse sémantique de la logique déontique. Nous analyserons de façon critique un texte de Schotch (1981) portant sur une interprétation de la logique déontique dans le cadre d’une sémantique non-kripkéenne. Nous laisserons de côté les choix relatifs à la syntaxe de son système afin de se concentrer sur l’analyse sémantique qu’il expose contre la logique déontique et sur celle qu’il propose en retour. Avant de voir le détail de son raisonnement, nous présenterons brièvement quelques notions de logique modale afin de faciliter la compréhension de l’argument de Schotch. Nous présenterons ensuite l’argument de l’auteur contre la logique déontique afin de pouvoir exposer sa solution, ce qui ouvrira la porte à une lecture critique de son analyse.

Broadband coaxial cavity resonator for complex permittivity measurements of liquids

A novel cavity perturbation technique using coaxial cavity resonators for the measurement of complex permittivity of liquids is presented. The method employs two types of resonators (Resonator I and Resonator II). Resonator I operates in the frequency range 600 MHz-7 GHz and resonator II operates in the frequency range 4 GHz-14 GHz. The introduction of the capillary tube filled with the sample liquid into the coaxial resonator causes shifts in the resonance frequency and loaded Q-factor of the resonator. The shifts in the resonance frequency and loaded Q-factor are used to determine the real and imaginary parts of the complex permittivity of the sample liquid, respectively. Using this technique, the dielectric parameters of water and nitrobenzene are measured. The results are compared with those obtained using other standard methods. The sources of errors are analyzed.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

RNS based programmable multi-mode decimation filter for WCDMA and WiMAX

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated

Decimation Filter Design Toolbox for Multi-Standard Wireless Transceivers using MATLAB.

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. A multi-standard design often involves extensive system level analysis and architectural partitioning, typically requiring extensive calculations. In this research, a decimation filter design tool for wireless communication standards consisting of GSM, WCDMA, WLANa, WLANb, WLANg and WiMAX is developed in MATLAB® using GUIDE environment for visual analysis. The user can select a required wireless communication standard, and obtain the corresponding multistage decimation filter implementation using this toolbox. The toolbox helps the user or design engineer to perform a quick design and analysis of decimation filter for multiple standards without doing extensive calculation of the underlying methods.

Automatic Image Annotation Using SURF Descriptors

In recent years there is an apparent shift in research from content based image retrieval (CBIR) to automatic image annotation in order to bridge the gap between low level features and high level semantics of images. Automatic Image Annotation (AIA) techniques facilitate extraction of high level semantic concepts from images by machine learning techniques. Many AIA techniques use feature analysis as the first step to identify the objects in the image. However, the high dimensional image features make the performance of the system worse. This paper describes and evaluates an automatic image annotation framework which uses SURF descriptors to select right number of features and right features for annotation. The proposed framework uses a hybrid approach in which k-means clustering is used in the training phase and fuzzy K-NN classification in the annotation phase. The performance of the system is evaluated using standard metrics.

Reinforcement Learning solution for Unit Commitment Problem through pursuit method

Unit commitment is an optimization task in electric power generation control sector. It involves scheduling the ON/OFF status of the generating units to meet the load demand with minimum generation cost satisfying the different constraints existing in the system. Numerical solutions developed are limited for small systems and heuristic methodologies find difficulty in handling stochastic cost functions associated with practical systems. This paper models Unit Commitment as a multi stage decision task and Reinforcement Learning solution is formulated through one efficient exploration strategy: Pursuit method. The correctness and efficiency of the developed solutions are verified for standard test systems

Ethernet Telemetry for Towed Arrays

The towed array electronics is essentially a multichannel real time data acquisition system. The major challenges involved in it are the simultaneous acquisition of data from multiple channels, telemetry of the data over tow cable (several kilometres in some systems) and synchronization with the onboard receiver for accurate reconstruction. A serial protocol is best suited to transmit the data to onboard electronics since number of wires inside the tow cable is limited. The best transmission medium for data over large distances is the optical fibre. In this a two step approach towards the realization of a reliable telemetry scheme for the sensor data using standard protocols is described. The two schemes are discussed in this paper. The first scheme is for conversion of parallel, time-multiplexed multi-sensor data to Ethernet. Existing towed arrays can be upgraded to ethernet using this scheme. Here the last lap of the transmission is by Ethernet over Fibre. For the next generation of towed arrays it is required to digitize and convert the data to ethernet close to the sensor. This is the second scheme. At the heart of this design is the Analog-to-Ethernet node. In addition to a more reliable interface, this helps in easier fault detection and firmware updates in the field for the towed arrays. The design challenges and considerations for incorporating a network of embedded devices within the array are highlighted