Chondrogenic Differentiation Alters the Immunosuppressive Property of Bone Marrow-Derived Mesenchymal Stem Cells, and the Effect is Partially due to the Upregulated Expression of B7 Molecules

To investigate the immunosuppressive properties of mesenchymal stem cells (MSCs), in the present study we examined the immunogenicity of undifferentiated and tri-lineage (chondrocytes, osteoblasts and adipocytes) differentiated rat bone marrow-derived MSCs under xenogeneic conditions. After chondrogenic-differentiation, rat bone marrow-derived MSCs stimulated human peripheral blood monocyte-derived DCs (hDCs), leading to 8- and 4-fold higher lymphocyte proliferation and cytotoxicity than that of undifferentiated MSCs. The Chondrogenic-differentiated MSCs were chemotactic to hDCs in Dunn chamber chemotaxis system and were rosetted by hDCs inrosette assays. Flow cytometry analysis revealed that chondrogenic-differentiated MSCs had promoted hDCs maturation causing higher CD83 expression in hDCs, whereas undifferentiated MSCs, osteogenic-and adipogenic-differentiated MSCs showed inhibitory effect on hDCs maturation. The co-stimulatory molecules B7 were up-regulated only in the chondrogenic-differentiated MSCs. After blocking B7 molecules with specific monoclonal antibodies in the chondrogenic-differentiated MSCs, CD83 expression of co-cultured hDCs was greatly reduced. In conclusion, chondrogenic differentiation may increase the immunogenicity of MSCs, leading to stimulation of DCs. The up-regulated expression of B7 molecules on the chondrogenic differentiated MSCs may be partially responsible for this event.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.