Dynamic Buffer Management for Multimedia Services in Beyond 3G Wireless Networks

This paper investigates a dynamic buffer man-agement scheme for QoS control of multimedia services in be-yond 3G wireless systems. The scheme is studied in the context of the state-of-the-art 3.5G system i.e. the High Speed Downlink Packet Access (HSDPA) which enhances 3G UMTS to support high-speed packet switched services. Unlike earlier systems, UMTS-evolved systems from HSDPA and beyond incorporate mechanisms such as packet scheduling and HARQ in the base station necessitating data buffering at the air interface. This introduces a potential bottleneck to end-to-end communication. Hence, buffer management at the air interface is crucial for end-to-end QoS support of multimedia services with multi-plexed parallel diverse flows such as video and data in the same end-user session. The dynamic buffer management scheme for HSDPA multimedia sessions with aggregated real-time and non real-time flows is investigated via extensive HSDPA simulations. The impact of the scheme on end-to-end traffic performance is evaluated with an example multimedia session comprising a real-time streaming flow concurrent with TCP-based non real-time flow. Results demonstrate that the scheme can guar-antee the end-to-end QoS of the real-time streaming flow, whilst simultaneously protecting the non real-time flow from starva-tion resulting in improved end-to-end throughput performance

Dynamic Buffer Management for Multimedia Services in 3.5G Wireless Networks

This paper presents and investigates a dynamic
buffer management scheme for QoS control of multimedia
services in a 3.5G wireless system i.e. the High Speed Downlink
Packet Access (HSDPA). HSDPA was introduced to enhance
UMTS for high-speed packet switched services. With HSDPA,
packet scheduling and HARQ mechanisms in the base station
require data buffering at the air interface thus introducing a
potential bottleneck to end-to-end communication. Hence, for
multimedia services with multiplexed parallel diverse flows
such as video and data in the same end-user session, buffer
management schemes in the base station are essential to support
end-to-end QoS provision. We propose a dynamic buffer management
scheme for HSDPA multimedia sessions with aggregated real-time and non real-time flows in the paper. The end-to-end performance impact of the scheme is evaluated with an example multimedia session comprising a real-time streaming
flow concurrent with TCP-based non real-time flow via extensive HSDPA simulations. Results demonstrate that the scheme can guarantee the end-to-end QoS of the real-time streaming flow, whilst simultaneously protecting non real-time flow from starvation resulting in improved end-to-end throughput performance

JPEG decoder implementation on FPGA using dynamic partial reconfiguration

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e telecomunicações

Efficient Transmitter/Receiver Architectures for High Performance Wireless Applications

The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.

Dynamic Traffic Grooming Algorithms for Reconfigurable SONET Over WDM Networks

The emergence of wavelength-division multiplexing (WDM) technology provides the capability for increasing the bandwidth of synchronous optical network (SONET) rings by grooming low-speed traffic streams onto different high-speed wavelength channels. Since the cost of SONET add–drop multiplexers (SADM) at each node dominates the total cost of these networks, how to assign the wavelength, groom the traffic, and bypass the traffic through the intermediate nodes has received a lot of attention from researchers recently. Moreover, the traffic pattern of the optical network changes from time to time. How to develop dynamic reconfiguration algorithms for traffic grooming is an important issue. In this paper, two cases (best fit and full fit) for handling reconfigurable SONET over WDM networks are proposed. For each approach, an integer linear programming model and heuristic algorithms (TS-1 and TS-2, based on the tabu search method) are given. The results demonstrate that the TS-1 algorithm can yield better solutions but has a greater running time than the greedy algorithm for the best fit case. For the full fit case, the tabu search heuristic yields competitive results compared with an earlier simulated annealing based method and it is more stable for the dynamic case.

Dynamic traffic grooming algorithms for reconfigurable SONET over WDM networks

The emergence of Wavelength Division Multiplexing (WDM) technology provides the capability for increasing the bandwidth of Synchronous Optical Network (SONET) rings by grooming low-speed traffic streams onto different high-speed wavelength channels. Since the cost of SONET add-drop multiplexers (SADM) at each node dominates the total cost of these networks, how to assign the wavelength, groom in the traffic and bypass the traffic through the intermediate nodes has received a lot of attention from researchers recently.

Dynamic analysis of the motorcycle chattering behaviour by means of symbolic multibody modelling

Aim of this research is the development and validation of a comprehensive multibody motorcycle model featuring rigid-ring tires, taking into account both slope and roughness of road surfaces. A novel parametrization for the general kinematics of the motorcycle is proposed, using a mixed reference-point and relative-coordinates approach. The resulting description, developed in terms of dependent coordinates, makes it possible to efficiently include rigid-ring kinematics as well as road elevation and slope. The equations of motion for the multibody system are derived symbolically and the constraint equations arising from the dependent-coordinate formulation are handled using a projection technique. Therefore the resulting system of equations can be integrated in time domain using a standard ODE algorithm. The model is validated with respect to maneuvers experimentally measured on the race track, showing consistent results and excellent computational efficiency. More in detail, it is also capable of reproducing the chatter vibration of racing motorcycles. The chatter phenomenon, appearing during high speed cornering maneuvers, consists of a self-excited vertical oscillation of both the front and rear unsprung masses in the range of frequency between 17 and 22 Hz. A critical maneuver is numerically simulated, and a self-excited vibration appears, consistent with the experimentally measured chatter vibration. Finally, the driving mechanism for the self-excitation is highlighted and a physical interpretation is proposed.

Sampling strategies for capillary isoelectric focusing with electroosmotic zone mobilization assessed by high-resolution dynamic computer simulation

The impact of initial sample distribution on separation and focusing of analytes in a pH 3–11 gradient formed by 101 biprotic carrier ampholytes under concomitant electroosmotic displacement was studied by dynamic high-resolution computer simulation. Data obtained with application of the analytes mixed with the carrier ampholytes (as is customarily done), as a short zone within the initial carrier ampholyte zone, sandwiched between zones of carrier ampholytes, or introduced before or after the initial carrier ampholyte zone were compared. With sampling as a short zone within or adjacent to the carrier ampholytes, separation and focusing of analytes is shown to proceed as a cationic, anionic, or mixed process and separation of the analytes is predicted to be much faster than the separation of the carrier components. Thus, after the initial separation, analytes continue to separate and eventually reach their focusing locations. This is different to the double-peak approach to equilibrium that takes place when analytes and carrier ampholytes are applied as a homogenous mixture. Simulation data reveal that sample application between two zones of carrier ampholytes results in the formation of a pH gradient disturbance as the concentration of the carrier ampholytes within the fluid element initially occupied by the sample will be lower compared to the other parts of the gradient. As a consequence thereof, the properties of this region are sample matrix dependent, the pH gradient is flatter, and the region is likely to represent a conductance gap (hot spot). Simulation data suggest that sample placed at the anodic side or at the anodic end of the initial carrier ampholyte zone are the favorable configurations for capillary isoelectric focusing with electroosmotic zone mobilization.

Dynamic & Cyclic behaviour of ballast in the long term as determined in Cedex's track box

The 6 cylinder servo-hydraulic loading system of CEDEX's track box (250 kN, 50 Hz) has been recently implemented with a new piezoelectric loading system (±20 kN, 300 Hz) allowing the incorporation of low amplitude high frequency dynamic load time histories to the high amplitude low frequency quasi-static load time histories used so far in the CEDEX's track box to assess the inelastic long term behavior of ballast under mixed traffic in conventional and high- speed lines. This presentation will discuss the results obtained in the first long-duration test performed at CEDEX's track box using simultaneously both loading systems, to simulate the pass-by of 6000 freight vehicles (1M of 225 kN axle loads) travelling at a speed of 120 km/h over a line with vertical irregularities corresponding to a medium quality lin3e level. The superstructure of the track tested at full scale consisted of E 60 rails, stiff rail pads (mayor que 450 kN/mm), B90.2 sleepers with USP 0.10 N/mm and a 0.35 m thick ballast layer of ADIF first class. A shear wave velocity of 250 m/s can be assumed for the different layers of the track sub-base. The ballast long-term settlements will be compared with those obtained in a previous long-duration quasi- static test performed in the same track, for the RIVAS [EU co-funded] project, in which no dynamic loads where considered. Also, the results provided by a high diameter cyclic triaxial cell with ballast tested in full size will be commented. Finally, the progress made at CEDEX's Geotechnical Laboratory to reproduce numerically the long term behavior of ballast will be discussed.

Analysis of the problems associated with dynamic interaction between train, track and structure at transition zones

El gran desarrollo experimentado por la alta velocidad en los principales países de la Unión Europea, en los últimos 30 años, hace que este campo haya sido y aún sea uno de los principales referentes en lo que a investigación se refiere. Por otra parte, la aparición del concepto super − alta velocidad hace que la investigación en el campo de la ingeniería ferroviaria siga adquiriendo importancia en los principales centros de investigación de los países en los que se desea implantar este modo de transporte, o en los que habiendo sido ya implantado, se pretenda mejorar. Las premisas de eficacia, eficiencia, seguridad y confort, que este medio de transporte tiene como razón de ser pueden verse comprometidas por diversos factores. Las zonas de transición, definidas en la ingeniería ferroviaria como aquellas secciones en las que se produce un cambio en las condiciones de soporte de la vía, pueden afectar al normal comportamiento para el que fue diseñada la infraestructura, comprometiendo seriamente los estándares de eficiencia en el tiempo de viaje, confort de los pasajeros y aumentando considerablemente los costes de mantenimiento de la vía, si no se toman las medidas oportunas. En esta tesis se realiza un estudio detallado de la zonas de transición, concretamente de aquellas en las que existe una cambio en la rigidez vertical de la vía debido a la presencia de un marco hidráulico. Para realizar dicho estudio se lleva a cabo un análisis numérico de interacción entre el vehículo y la estructura, con un modelo bidimensional de elemento finitos, calibrado experimentalmente, en estado de tensión plana. En este análisis se tiene en cuenta el efecto de las irregularidades de la vía y el comportamiento mecánico de la interfaz suelo-estructura, con el objetivo de reproducir de la forma más real posible el efecto de interacción entre el vehículo, la vía y la estructura. Otros efectos como la influencia de la velocidad del tren y los asientos diferenciales, debidos a deformaciones por consolidación de los terraplenes a ambos lados el marco hidráulico, son también analizados en este trabajo. En esta tesis, los cálculos de interacción se han llevado a cabo en dos fases diferentes. En la primera, se ha considerado una interacción sencilla debida al paso de un bogie de un tren Eurostar. Los cálculos derivados de esta fase se han denominado cálculos a corto plazo. En la segunda, se ha realizado un análisis considerando múltiples pasos de bogie del tren Eurostar, conformando un análisis de degradación en el que se tiene en cuenta, en cada ciclo, la deformación de la capa de balasto. Los cálculos derivados de esta fase, son denominados en el texto como cálculos a largo plazo. Los resultados analizados muestran que la utilización de los denominados elementos de contacto es fundamental cuando se desea estudiar la influencia de asientos diferenciales, especialmente en transiciones terraplén-estructura en las que la cuña de cimentación no llega hasta la base de cimentación de la estructura. Por otra parte, tener en cuenta los asientos del terraplén, es sumamente importante, cuando se desea realizar un análisis de degradación de la vía ya que su influencia en la interacción entre el vehículo y la vía es muy elevada, especialmente para valores altos de velocidad del tren. En cuanto a la influencia de las irregularidades de la vía, en los cálculos efectuados, se revela que su importancia es muy notable, siendo su influencia muy destacada cuanto mayor sea la velocidad del tren. En este punto cabe destacar la diferencia de resultados derivada de la consideración de perfiles de irregularidades de distinta naturaleza. Los resultados provenientes de considerar perfiles artificiales son en general muy elevados, siendo estos más apropiados para realizar estudios de otra índole, como por ejemplo de seguridad al descarrilamiento. Los resultados provenientes de perfiles reales, dados por diferentes Administradores ferroviarios, presentan resultados menos elevados y más propios del problema analizar. Su influencia en la interacción dinámica entre el vehículo y la vía es muy importante, especialmente para velocidades elevadas del tren. Además el fenómeno de degradación conocido como danza de traviesas, asociado a zonas de transición, es muy susceptible a la consideración de irregularidades de la vía, tal y como se desprende de los cálculos efectuados a largo plazo. The major development experienced by high speed in the main countries of the European Union, in the last 30 years, makes railway research one of the main references in the research field. It should also be mentioned that the emergence of the concept superhigh − speed makes research in the field of Railway Engineering continues to gain importance in major research centers in the countries in which this mode of transportation is already implemented or planned to be implemented. The characteristics that this transport has as rationale such as: effectiveness, efficiency, safety and comfort, may be compromised by several factors. The transition zones are defined in railway engineering as a region in which there is an abrupt change of track stiffness. This stiffness variation can affect the normal behavior for which the infrastructure has been designed, seriously compromising efficiency standards in the travel time, passenger comfort and significantly increasing the costs of track maintenance, if appropriate measures are not taken. In this thesis a detailed study of the transition zones has been performed, particularly of those in which there is a change in vertical stiffness of the track due to the presence of a reinforced concrete culvert. To perform such a study a numerical interaction analysis between the vehicle, the track and the structure has been developed. With this purpose a two-dimensional finite element model, experimentally calibrated, in a state of plane stress, has been used. The implemented numerical models have considered the effects of track irregularities and mechanical behavior of soil-structure interface, with the objective of reproducing as accurately as possible the dynamic interaction between the vehicle the track and the structure. Other effects such as the influence of train speed and differential settlement, due to secondary consolidation of the embankments on both sides of culvert, have also been analyzed. In this work, the interaction analysis has been carried out in two different phases. In the first part a simple interaction due to the passage of a bogie of a Eurostar train has been considered. Calculations derived from this phase have been named short-term analysis. In the second part, a multi-load assessment considering an Eurostar train bogie moving along the transition zone, has been performed. The objective here is to simulate a degradation process in which vertical deformation of the ballast layer was considered. Calculations derived from this phase have been named long-term analysis. The analyzed results show that the use of so-called contact elements is essential when one wants to analyze the influence of differential settlements, especially in embankment-structure transitions in which the wedge-shaped backfill does not reach the foundation base of the structure. Moreover, considering embankment settlement is extremely important when it is desired to perform an analysis of track degradation. In these cases the influence on the interaction behaviour between the vehicle and the track is very high, especially for higher values of speed train. Regarding the influence of the track irregularities, this study has proven that the track’s dynamic response is heavily influenced by the irregularity profile and that this influence is more important for higher train velocities. It should also be noted that the difference in results derived from consideration of irregularities profiles of different nature. The results coming from artificial profiles are generally very high, these might be more appropriate in order to study other effects, such as derailment safety. Results from real profiles, given by the monitoring works of different rail Managers, are softer and they fit better to the context of this thesis. The influence of irregularity profiles on the dynamic interaction between the train and the track is very important, especially for high-speeds of the train. Furthermore, the degradation phenomenon known as hanging sleepers, associated with transition zones, is very susceptible to the consideration of track irregularities, as it can be concluded from the long-term analysis.

Output Impedance Correction Circuit (OICC): A New Concept to Improve the Dynamic Response of DC/DC Converters with Additional Energy Path

El desarrollo da las nuevas tecnologías permite a los ingenieros llevar al límite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la información a una alta velocidad, con un alto consumo de energía, o esperar en modo de baja potencia con el mínimo consumo posible. Esta gran variación en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del Módulo de Regulador de Tensión (Voltage Regulated Module, VRM) que alimenta al IC. Además, las características adicionales obligatorias, tales como adaptación del nivel de tensión (Adaptive Voltage Positioning, AVP) y escalado dinámico de la tensión (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el diseño de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energía y el rendimiento durante la operación de DVS. Por tanto, las actuales tendencias de investigación se centran en mejorar la respuesta dinámica del VRM, mientras se reduce el tamaño del condensador de salida. La reducción del condensador de salida lleva a menor coste y una prolongación de la vida del sistema ya que se podría evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar más rápido y con menor estrés de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensión de salida es menor. El comportamiento dinámico del sistema con un control lineal (Control Modo Tensión, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,…) está limitado por la frecuencia de conmutación del convertidor y por el tamaño del filtro de salida. La reducción del condensador de salida se puede lograr incrementando la frecuencia de conmutación, así como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo régimen permanente en un tiempo mínimo, así como el filtro de salida, más específicamente la pendiente de la corriente de la bobina, define la respuesta de la tensión de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega más rápido al nuevo régimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tránsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de pérdidas de conmutación y las corrientes RMS. Para conseguir tanto la reducción del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones dinámicas, un convertidor multifase es adoptado como estándar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitación impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificación topológica (Topologic modifications) de la etapa básica de potencia para incrementar la pendiente de la corriente de bobina y así reducir la duración de tránsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escalón de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviación de la tensión de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energía (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duración del transitorio y la desviación de la tensión de salida. De esta manera, durante el régimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es diseñado para trabajar con una frecuencia de conmutación moderada para conseguir requisitos estáticos. Por otro lado, el comportamiento dinámico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de pérdidas durante el transitorio. Por otro lado, la implementación del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutación, aunque produce menores pérdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicación, la implementación y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una solución ofrece más ventajas que las otras, pero también unas desventajas. En general, un sistema con AEP ideal debería tener las siguientes propiedades: 1. El impacto del AEP a las pérdidas del sistema debería ser mínimo. A lo largo de la operación, el AEP genera pérdidas adicionales, con lo cual, en el caso ideal, el AEP debería trabajar por un pequeño intervalo de tiempo, solo durante los tránsitos; la otra opción es tener el AEP constantemente activo pero, por la compensación del rizado de la corriente de bobina, se generan pérdidas innecesarias. 2. El AEP debería ser activado inmediatamente para minimizar la desviación de la tensión de salida. Para conseguir una activación casi instantánea, el sistema puede ser informado por la carga antes del escalón o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que actúa a la perturbación de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensión de salida, logrando una menor desviación de la tensión de salida. 3. El AEP debería ser desactivado una vez que el nuevo régimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayoría de las soluciones de SoA estiman la duración del transitorio, que puede provocar un transitorio adicional si la estimación no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo régimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como mínimo un subsistema, o bien el convertidor principal o el AEP, debería operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los parásitos. Además, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con mínimo tiempo, así reducen la duración del transitorio y tienen un impacto menor a las pérdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y parásitos de los componentes. 5. El AEP debería inyectar la corriente a la salida en una manera controlada, así se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensión de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es diseñado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensión de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbación de tensión de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con histéresis, la corriente auxiliar tiene el control con prealimentación (feed-forward) de tensión de entrada y la corriente es definida y limitada. Por otro lado, si la solución utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensión de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma más/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estrés térmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementación con solo una fase. Esta tesis propone un nuevo método de control del flujo de energía por el AEP y el convertidor principal. El concepto propuesto se basa en la inyección controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador físico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor síncrono multifase con control modo de corriente CMC (incluyendo e implementación con una fase) y puede operar con la tensión de salida constante o con AVP. Además, el concepto es extendido a un convertidor de una fase con control modo de tensión VMC. Durante la operación, el control de tensión de salida de convertidor principal y control de corriente del subsistema OICC están siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los parásitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Según el método de control propuesto, el sistema se puede encontrar en dos estados: durante el régimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC está activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma autónoma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo régimen permanente es detectado, observando las variables del estado. La validación del concepto OICC es hecha aplicándolo a un convertidor tipo reductor síncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140μF, mientras el factor de multiplicación n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor síncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducción de la desviación de tensión de salida con factor 12, tanto con funcionamiento básico como con funcionamiento AVP. Además, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida físico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento dinámico. Más aun, se ha cuantificado el impacto en las pérdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las pérdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo último, el condensador de salida de sistema con OICC es mucho más pequeño que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energía se incrementa. En resumen, las contribuciones principales de la tesis son: • El concepto propuesto de Output Impedance Correction Circuit (OICC), • El control a nivel de sistema basado en el método usado para cambiar los estados de operación, • La implementación del subsistema OICC en lazo cerrado conjunto con la implementación del convertidor principal, • La cuantificación de las perdidas dinámicas bajo la carga pulsante y bajo la operación DVS, y • La robustez del sistema bajo la variación del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,…) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140μF output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: • The proposed Output Impedance Correction Circuit (OICC) concept, • The system level control based on the used approach to change the states of operation, • The OICC subsystem closed-loop implementation, together with the main converter implementation, • The dynamic losses under the pulsating load and the DVS operation quantification, and • The system robustness on the capacitor impedance variation and consecutive load-steps.

Dynamic Movements of Organelles Containing Niemann-Pick C1 Protein: NPC1 Involvement in Late Endocytic EventsV⃞

People homozygous for mutations in the Niemann-Pick type C1 (NPC1) gene have physiological defects, including excess accumulation of intracellular cholesterol and other lipids, that lead to drastic neural and liver degeneration. The NPC1 multipass transmembrane protein is resident in late endosomes and lysosomes, but its functions are unknown. We find that organelles containing functional NPC1-fluorescent protein fusions undergo dramatic movements, some in association with extending strands of endoplasmic reticulum. In NPC1 mutant cells the NPC1-bearing organelles that normally move at high speed between perinuclear regions and the periphery of the cell are largely absent. Pulse-chase experiments with dialkylindocarbocyanine low-density lipoprotein showed that NPC1 organelles function late in the endocytic pathway; NPC1 protein may aid the partitioning of endocytic and lysosomal compartments. The close connection between NPC1 and the drug U18666A, which causes NPC1-like organelle defects, was established by rescuing drug-treated cells with overproduced NPC1. U18666A inhibits outward movements of NPC1 organelles, trapping membranes and cholesterol in perinuclear organelles similar to those in NPC1 mutant cells, even when cells are grown in lipoprotein-depleted serum. We conclude that NPC1 protein promotes the creation and/or movement of particular late endosomes, which rapidly transport materials to and from the cell periphery.

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

Visual control of robots : high-performance visual servoing

The application of high-speed machine vision for close-loop position control, or visual servoing, of a robot manipulator. It provides a comprehensive coverage of all aspects of the visual servoing problem: robotics, vision, control, technology and implementation issues. While much of the discussion is quite general the experimental work described is based on the use of a high-speed binary vision system with a monocular "eye-in-hand" camera.