A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to (gm)-C filters

A linearly tunable low-voltage CMOS transconductor featuring a new adaptative-bias mechanism that considerably improves the stability of the processed-signal common,mode voltage over the tuning range, critical for very-low voltage applications, is introduced. It embeds a feedback loop that holds input devices on triode region while boosting the output resistance. Analysis of the integrator frequency response gives an insight into the location of secondary poles and zeros as function of design parameters. A third-order low-pass Cauer filter employing the proposed transconductor was designed and integrated on a 0.8-mum n-well CMOS standard process. For a 1.8-V supply, filter characterization revealed f(p) = 0.93 MHz, f(s) = 1.82 MHz, A(min) = 44.08, dB, and A(max) = 0.64 dB at nominal tuning. Mined by a de voltage V-TUNE, the filter bandwidth was linearly adjusted at a rate of 11.48 kHz/mV over nearly one frequency decade. A maximum 13-mV deviation on the common-mode voltage at the filter output was measured over the interval 25 mV less than or equal to V-TUNE less than or equal to 200 mV. For V-out = 300 mV(pp) and V-TUNE = 100 mV, THD was -55.4 dB. Noise spectral density was 0.84 muV/Hz(1/2) @1 kHz and S/N = 41 dB @ V-out = 300 mV(pp) and 1-MHz bandwidth. Idle power consumption was 1.73 mW @V-TUNE = 100 mV. A tradeoff between dynamic range, bandwidth, power consumption, and chip area has then been achieved.

A low-voltage programmable-gain current-mode amplifier

A CMOS low-voltage, wide-band continuous-time current amplifier is presented. Based on an open-loop topology, the circuit is composed by transresistance and transconductance stages built around triode-operating transistors. In addition to an extended dynamic range, the amplifier gain can be programmed within good accuracy by the rapport between the aspect-ratio of such transistors and tuning biases Vxand Vy. A balanced current-amplifier according to a single I. IV-supply and a 0.35μm fabrication process is designed. Simulated results from PSPiCE and Bsm3v3 models indicate a programmable gain within the range 20-34dB and a minimum break-frequency of IMHz @CL=IpF. For a 200 μApp-level, THD is 0.8% and 0.9% at IKHz and 100KHz, respectively. Input noise is 405pA√Hz @20dB-gain, which gives a SNR of 66dB @1MHz-bandwidth. Maximum quiescent power consumption is 56μ W. © 2002 IEEE.

Influence of the supply of reactive power in the calculation of the transfer capability

This paper presents some initial concepts for including reactive power in linear methods for computing Available Transfer Capability (ATC). It is proposed an approximation for the reactive power flows computation that uses the exact circle equations for the transmission line complex flow, and then it is determined the ATC using active power distribution factors. The transfer capability can be increased using the sensitivities of flow that show the best group of buses which can have their reactive power injection modified in order to remove the overload in the transmission lines. The results of the ATC computation and of the use of the sensitivities of flow are presented using the Cigré 32-bus system. © 2004 IEEE.

Discrete-time sliding mode control of input-delay systems applied on a power generation system

This paper presents two discrete sliding mode control (SMC) design. The first one is a discrete-time SMC design that doesn't take into account the time-delay. The second one is a discrete-time SMC design, which takes in consideration the time-delay. The proposed techniques aim at the accomplishment simplicity and robustness for an uncertainty class. Simulations results are shown and the effectiveness of the used techniques is analyzed. © 2006 IEEE.

A comparison of performance indexes in DC-DC converters under different stabilizing state-dependent switching laws

This paper deals with the problem of establishing stabilizing state-dependent switching laws in DC-DC converters operating at continuous conduction mode (CCM) and comparing their performance indexes. Firstly, the nature of the problem is defined, that is, the study of switched affine systems, which may not share a common equilibrium point. The concept of stability is, therefore, broadened. Then, the central theorem is proposed, from which a family of switching laws can be derived, namely the minimum law and the hold state law. Some of these are proved to stabilize the basic DC-DC converters and then, their performances are compared to another law, from a previous work, by simulation, where a great reduction in overshoot is obtained. © 2011 IEEE.

A DC-DC converter based on the three-state switching cell for high current and voltage step-down applications

This paper presents a pulsewidth modulation dc-dc nonisolated buck converter using the three-state switching cell, constituted by two active switches, two diodes, and two coupled inductors. Only part of the load power is processed by the active switches, reducing the peak current through the switches to half of the load current, as higher power levels can then be achieved by the proposed topology. The volume of reactive elements, i.e., inductors and capacitors, is also decreased since the ripple frequency of the output voltage is twice the switching frequency. Due to the intrinsic characteristics of the topology, total losses are distributed among all semiconductors. Another advantage of this converter is the reduced region for discontinuous conduction mode when compared to the conventional buck converter or, in other words, the operation range in continuous conduction mode is increased, as demonstrated by the static gain plot. The theoretical approach is detailed through qualitative and quantitative analyses by the application of the three-state switching cell to the buck converter operating in nonoverlapping mode $(D < 0.5)$. Besides, the mathematical analysis and development of an experimental prototype rated at 1 kW are carried out. The main experimental results are presented and adequately discussed to clearly identify its claimed advantages. © 1986-2012 IEEE.

The public corporation: an adequate instrument for the supply of electric power

Includes bibliography

Comparative analysis between overlapping and non-overlapping operation modes for the PWM buck converter using the three-state switching cell

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

A novel single-phase ZCS-PWM high power factor boost rectifier

This paper presents a novel single-phase high power factor PWM boost rectifier, featuring soft commutation of the active switches at zero-current (ZCS). It incorporates the most desirable properties of the conventional PWM and the soft-switching resonant techniques. The input current shaping is achieved with average current mode control, and continuous inductor current mode. This new PWM converter provides ZCS turn-on and turn-off of the active switches, and it is suitable for high power applications employing IGBTs. Principle of operation, theoretical analysis, a design example, and experimental results from a laboratory prototype rated at 1600 W with 400 Vdc output voltage are presented. The measured efficiency and power factor were 96.2% and 0.99 respectively, with an input current THD equal to 3.94%, for an input voltage THD equal to 3.8%, at rated load.

Switching the mode of sucrose utilization by Saccharomyces cerevisiae

Abstract Background Overflow metabolism is an undesirable characteristic of aerobic cultures of Saccharomyces cerevisiae during biomass-directed processes. It results from elevated sugar consumption rates that cause a high substrate conversion to ethanol and other bi-products, severely affecting cell physiology, bioprocess performance, and biomass yields. Fed-batch culture, where sucrose consumption rates are controlled by the external addition of sugar aiming at its low concentrations in the fermentor, is the classical bioprocessing alternative to prevent sugar fermentation by yeasts. However, fed-batch fermentations present drawbacks that could be overcome by simpler batch cultures at relatively high (e.g. 20 g/L) initial sugar concentrations. In this study, a S. cerevisiae strain lacking invertase activity was engineered to transport sucrose into the cells through a low-affinity and low-capacity sucrose-H+ symport activity, and the growth kinetics and biomass yields on sucrose analyzed using simple batch cultures. Results We have deleted from the genome of a S. cerevisiae strain lacking invertase the high-affinity sucrose-H+ symporter encoded by the AGT1 gene. This strain could still grow efficiently on sucrose due to a low-affinity and low-capacity sucrose-H+ symport activity mediated by the MALx1 maltose permeases, and its further intracellular hydrolysis by cytoplasmic maltases. Although sucrose consumption by this engineered yeast strain was slower than with the parental yeast strain, the cells grew efficiently on sucrose due to an increased respiration of the carbon source. Consequently, this engineered yeast strain produced less ethanol and 1.5 to 2 times more biomass when cultivated in simple batch mode using 20 g/L sucrose as the carbon source. Conclusion Higher cell densities during batch cultures on 20 g/L sucrose were achieved by using a S. cerevisiae strain engineered in the sucrose uptake system. Such result was accomplished by effectively reducing sucrose uptake by the yeast cells, avoiding overflow metabolism, with the concomitant reduction in ethanol production. The use of this modified yeast strain in simpler batch culture mode can be a viable option to more complicated traditional sucrose-limited fed-batch cultures for biomass-directed processes of S. cerevisiae.

Mode-locked diode-pumped vanadate lasers operated with PbS quantum dots

The use of glasses doped with PbS nanocrystals as intracavity saturable absorbers for passive Q-switching and mode locking of c-cut Nd:Gd0.7Y0.3VO4, Nd:YVO4, and Nd:GdVO4 lasers is investigated. Q-switching yields pulses as short as 35 ns with an average output power of 435 mW at a repetition rate of 6–12 kHz at a pump power of 5–6 W. Mode locking through a combination of PbS nanocrystals and a Kerr lens results in 1.4 ps long pulses with an average output power of 255 mW at a repetition rate of 100 MHz.

High-peak-power pulse generation from a monolithic master oscillator power amplifier at 1.5 μm

We present an experimental study on the generation of high-peak-power short optical pulses from a fully integrated master-oscillator power-amplifier emitting at 1.5 μm. High-peak-power (2.7 W) optical pulses with short duration (100 ps) have been generated by gain switching the master oscillator under optimized driving conditions. The static and dynamic characteristics of the device have been studied as a function of the driving conditions. The ripples appearing in the power-current characteristics under cw conditions have been attributed to mode hopping between the master oscillator resonant mode and the Fabry-Perot modes of the entire device cavity. Although compound cavity effects have been evidenced to affect the static and dynamic performance of the device, we have demonstrated that trains of single-mode short optical pulses at gigahertz frequencies can be conveniently generated in these devices.

Comparison of V2IC control with voltage mode and current mode controls for high frequency (MHz) and very fast response applications

High switching frequencies (several MHz) allow the integration of low power DC/DC converters. Although, in theory, a high switching frequency would make possible to implement a conventional Voltage Mode control (VMC) or Peak Current Mode control (PCMC) with very high bandwidth, in practice, parasitic effects and robustness limits the applicability of these control techniques. This paper compares VMC and CMC techniques with the V2IC control. This control is based on two loops. The fast internal loop has information of the output capacitor current and the error voltage, providing fast dynamic response under load and voltage reference steps, while the slow external voltage loop provides accurate steady state regulation. This paper shows the fast dynamic response of the V2IC control under load and output voltage reference steps and its robustness operating with additional output capacitors added by the customer.

Analysis of mode competition in a monolithic master- oscillator power‐amplifier emitting at 1.5 μm

The optical and radio-frequency spectra of a monolithic master-oscillator power-amplifier emitting at 1.5 ?m have been analyzed in a wide range of steady-state injection conditions. The analysis of the spectral maps reveals that, under low injection current of the master oscillator, the device operates in two essentially different operation modes depending on the current injected into the amplifier section. The regular operation mode with predominance of the master oscillator alternates with lasing of the compound cavity modes allowed by the residual reflectance of the amplifier front facet. The quasi-periodic occurrence of these two regimes as a function of the amplifier current has been consistently interpreted in terms of a thermally tuned competition between the modes of the master oscillator and the compound cavity modes.

Wide bandwidth envelope trackers with reduced switching frequency for RF power amplifier

El requerimiento de proveer alta frecuencia de datos en los modernos sistema de comunicación inalámbricos resulta en complejas señales moduladas de radio-frequencia (RF) con un gran ancho de banda y alto ratio pico-promedio (PAPR). Para garantizar la linealidad del comportamiento, los amplificadores lineales de potencia comunes funcionan típicamente entre 4 y 10 dB de back-o_ desde la máxima potencia de salida, ocasionando una baja eficiencia del sistema. La eliminación y restauración de la evolvente (EER) y el seguimiento de la evolvente (ET) son dos prometedoras técnicas para resolver el problema de la eficiencia. Tanto en EER como en ET, es complicado diseñar un amplificador de potencia que sea eficiente para señales de RF de alto ancho de banda y alto PAPR. Una propuesta común para los amplificadores de potencia es incluir un convertidor de potencia de muy alta eficiencia operando a frecuencias más altas que el ancho de banda de la señal RF. En este caso, la potencia perdida del convertidor ocasionado por la alta frecuencia desaconseja su práctica cuando el ancho de banda es muy alto. La solución a este problema es el enfoque de esta disertación que presenta dos arquitecturas de amplificador evolvente: convertidor híbrido-serie con una técnica de evolvente lenta y un convertidor multinivel basado en un convertidor reductor multifase con control de tiempo mínimo. En la primera arquitectura, una topología híbrida está compuesta de una convertidor reductor conmutado y un regulador lineal en serie que trabajan juntos para ajustar la tensión de salida para seguir a la evolvente con precisión. Un algoritmo de generación de una evolvente lenta crea una forma de onda con una pendiente limitada que es menor que la pendiente máxima de la evolvente original. La salida del convertidor reductor sigue esa forma de onda en vez de la evolvente original usando una menor frecuencia de conmutación, porque la forma de onda no sólo tiene una pendiente reducida sino también un menor ancho de banda. De esta forma, el regulador lineal se usa para filtrar la forma de onda tiene una pérdida de potencia adicional. Dependiendo de cuánto se puede reducir la pendiente de la evolvente para producir la forma de onda, existe un trade-off entre la pérdida de potencia del convertidor reductor relacionada con la frecuencia de conmutación y el regulador lineal. El punto óptimo referido a la menor pérdida de potencia total del amplificador de evolvente es capaz de identificarse con la ayuda de modelo preciso de pérdidas que es una combinación de modelos comportamentales y analíticos de pérdidas. Además, se analiza el efecto en la respuesta del filtro de salida del convertidor reductor. Un filtro de dampeo paralelo extra es necesario para eliminar la oscilación resonante del filtro de salida porque el convertidor reductor opera en lazo abierto. La segunda arquitectura es un amplificador de evolvente de seguimiento de tensión multinivel. Al contrario que los convertidores que usan multi-fuentes, un convertidor reductor multifase se emplea para generar la tensión multinivel. En régimen permanente, el convertidor reductor opera en puntos del ciclo de trabajo con cancelación completa del rizado. El número de niveles de tensión es igual al número de fases de acuerdo a las características del entrelazamiento del convertidor reductor. En la transición, un control de tiempo mínimo (MTC) para convertidores multifase es novedosamente propuesto y desarrollado para cambiar la tensión de salida del convertidor reductor entre diferentes niveles. A diferencia de controles convencionales de tiempo mínimo para convertidores multifase con inductancia equivalente, el propuesto MTC considera el rizado de corriente por cada fase basado en un desfase fijo que resulta en diferentes esquemas de control entre las fases. La ventaja de este control es que todas las corrientes vuelven a su fase en régimen permanente después de la transición para que la siguiente transición pueda empezar muy pronto, lo que es muy favorable para la aplicación de seguimiento de tensión multinivel. Además, el control es independiente de la carga y no es afectado por corrientes de fase desbalanceadas. Al igual que en la primera arquitectura, hay una etapa lineal con la misma función, conectada en serie con el convertidor reductor multifase. Dado que tanto el régimen permanente como el estado de transición del convertidor no están fuertemente relacionados con la frecuencia de conmutación, la frecuencia de conmutación puede ser reducida para el alto ancho de banda de la evolvente, la cual es la principal consideración de esta arquitectura. La optimización de la segunda arquitectura para más alto anchos de banda de la evolvente es presentada incluyendo el diseño del filtro de salida, la frecuencia de conmutación y el número de fases. El área de diseño del filtro está restringido por la transición rápida y el mínimo pulso del hardware. La rápida transición necesita un filtro pequeño pero la limitación del pulso mínimo del hardware lleva el diseño en el sentido contrario. La frecuencia de conmutación del convertidor afecta principalmente a la limitación del mínimo pulso y a las pérdidas de potencia. Con una menor frecuencia de conmutación, el ancho de pulso en la transición es más pequeño. El número de fases relativo a la aplicación específica puede ser optimizado en términos de la eficiencia global. Otro aspecto de la optimización es mejorar la estrategia de control. La transición permite seguir algunas partes de la evolvente que son más rápidas de lo que el hardware puede soportar al precio de complejidad. El nuevo método de sincronización de la transición incrementa la frecuencia de la transición, permitiendo que la tensión multinivel esté más cerca de la evolvente. Ambas estrategias permiten que el convertidor pueda seguir una evolvente con un ancho de banda más alto que la limitación de la etapa de potencia. El modelo de pérdidas del amplificador de evolvente se ha detallado y validado mediante medidas. El mecanismo de pérdidas de potencia del convertidor reductor tiene que incluir las transiciones en tiempo real, lo cual es diferente del clásico modelos de pérdidas de un convertidor reductor síncrono. Este modelo estima la eficiencia del sistema y juega un papel muy importante en el proceso de optimización. Finalmente, la segunda arquitectura del amplificador de evolvente se integra con el amplificador de clase F. La medida del sistema EER prueba el ahorro de energía con el amplificador de evolvente propuesto sin perjudicar la linealidad del sistema. ABSTRACT The requirement of delivering high data rates in modern wireless communication systems results in complex modulated RF signals with wide bandwidth and high peak-to-average ratio (PAPR). In order to guarantee the linearity performance, the conventional linear power amplifiers typically work at 4 to 10 dB back-off from the maximum output power, leading to low system efficiency. The envelope elimination and restoration (EER) and envelope tracking (ET) are two promising techniques to overcome the efficiency problem. In both EER and ET, it is challenging to design efficient envelope amplifier for wide bandwidth and high PAPR RF signals. An usual approach for envelope amplifier includes a high-efficiency switching power converter operating at a frequency higher than the RF signal's bandwidth. In this case, the power loss of converter caused by high switching operation becomes unbearable for system efficiency when signal bandwidth is very wide. The solution of this problem is the focus of this dissertation that presents two architectures of envelope amplifier: a hybrid series converter with slow-envelope technique and a multilevel converter based on a multiphase buck converter with the minimum time control. In the first architecture, a hybrid topology is composed of a switched buck converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. A slow envelope generation algorithm yields a waveform with limited slew rate that is lower than the maximum slew rate of the original envelope. The buck converter's output follows this waveform instead of the original envelope using lower switching frequency, because the waveform has not only reduced slew rate but also reduced bandwidth. In this way, the linear regulator used to filter the waveform has additional power loss. Depending on how much reduction of the slew rate of envelope in order to obtain that waveform, there is a trade-off between the power loss of buck converter related to the switching frequency and the power loss of linear regulator. The optimal point referring to the lowest total power loss of this envelope amplifier is identified with the help of a precise power loss model that is a combination of behavioral and analytic loss model. In addition, the output filter's effect on the response is analyzed. An extra parallel damping filter is needed to eliminate the resonant oscillation of output filter L and C, because the buck converter operates in open loop. The second architecture is a multilevel voltage tracking envelope amplifier. Unlike the converters using multi-sources, a multiphase buck converter is employed to generate the multilevel voltage. In the steady state, the buck converter operates at complete ripple cancellation points of duty cycle. The number of the voltage levels is equal to the number of phases according the characteristics of interleaved buck converter. In the transition, a minimum time control (MTC) for multiphase converter is originally proposed and developed for changing the output voltage of buck converter between different levels. As opposed to conventional minimum time control for multiphase converter with equivalent inductance, the proposed MTC considers the current ripple of each phase based on the fixed phase shift resulting in different control schemes among the phases. The advantage of this control is that all the phase current return to the steady state after the transition so that the next transition can be triggered very soon, which is very favorable for the application of multilevel voltage tracking. Besides, the control is independent on the load condition and not affected by the unbalance of phase current. Like the first architecture, there is also a linear stage with the same function, connected in series with the multiphase buck converter. Since both steady state and transition state of the converter are not strongly related to the switching frequency, it can be reduced for wide bandwidth envelope which is the main consideration of this architecture. The optimization of the second architecture for wider bandwidth envelope is presented including the output filter design, switching frequency and the number of phases. The filter design area is restrained by fast transition and the minimum pulse of hardware. The fast transition needs small filter but the minimum pulse of hardware limitation pushes the filter in opposite way. The converter switching frequency mainly affects the minimum pulse limitation and the power loss. With lower switching frequency, the pulse width in the transition is smaller. The number of phases related to specific application can be optimized in terms of overall efficiency. Another aspect of optimization is improving control strategy. Transition shift allows tracking some parts of envelope that are faster than the hardware can support at the price of complexity. The new transition synchronization method increases the frequency of transition, allowing the multilevel voltage to be closer to the envelope. Both control strategies push the converter to track wider bandwidth envelope than the limitation of power stage. The power loss model of envelope amplifier is detailed and validated by measurements. The power loss mechanism of buck converter has to include the transitions in real time operation, which is different from classical power loss model of synchronous buck converter. This model estimates the system efficiency and play a very important role in optimization process. Finally, the second envelope amplifier architecture is integrated with a Class F amplifier. EER system measurement proves the power saving with the proposed envelope amplifier without disrupting the linearity performance.