The transformation of work? A quantitative evaluation of changes in work in Portugal

This report is made for the Work Package 15 of WORKS project and tries to develop more information on the Portuguese situation in the work structures changes in the recent years. It starts with an analysis of socio- economical indicators (Macro economical indicators, Employment indicators, Consumption, Technology at the workplace, Productivity), and then approaches the situation in terms of work flexibility in its dimensions of time use and New forms of work organisation. It traces employment in business functions with a sectoral and occupational approach, and analyses the occupational change in South Europe with particular relevance to Portugal (skill utilisation and job satisfaction, occupational and industrial mobility, quantitative evaluation of the shape of employment in Europe. Finaly are analysed the globalisation indicators.

A promoção da flexibilidade com alunos do 1º ano da Escola de Dança do Orfeão de Leiria

Relatório Final de Estágio apresentado à Escola Superior de Dança com vista à obtenção do Grau de Mestre em Ensino de Dança.

Psychological well-being and perception of disease severity in people with multiple sclerosis, who underwent a program of self-regulation to promote physical activity

Rehabilitation is very important for in the results of treatment in individuals with multiple sclerosis. Rehabilitation processes occur through gradual changes. These changes integrate intrinsic and extrinsic mechanisms of the individual, promoting adaptations to the needs and activities of daily living according to individual goals. Recommendations for exercise in multiple sclerosis: these recommendations apply only to patients with EDSS less than 7; moderate intensity aerobic exercise for a total of 20 to 30 minutes, twice or three times for week; the resistance training with low or moderate intensity is well tolerated by patients with MS; associated with these exercises were recommended flexibility exercises of moderate intensity, as well as strengthening exercises. The aim of this study is to examine the implications of the program of self-regulation in the perception of illness and mental health (psychological well-being domain) in multiple sclerosis patients.

A comprehensive simulation study of slotted CSMA/CA for IEEE 802.15.4 wireless sensor networks

In this paper, we analyze the performance limits of the slotted CSMA/CA mechanism of IEEE 802.15.4 in the beacon-enabled mode for broadcast transmissions in WSNs. The motivation for evaluating the beacon-enabled mode is due to its flexibility for WSN applications as compared to the non-beacon enabled mode. Our analysis is based on an accurate simulation model of the slotted CSMA/CA mechanism on top of a realistic physical layer, with respect to the IEEE 802.15.4 standard specification. The performance of the slotted CSMA/CA is evaluated and analyzed for different network settings to understand the impact of the protocol attributes (superframe order, beacon order and backoff exponent) on the network performance, namely in terms of throughput (S), average delay (D) and probability of success (Ps). We introduce the concept of utility (U) as a combination of two or more metrics, to determine the best offered load range for an optimal behavior of the network. We show that the optimal network performance using slotted CSMA/CA occurs in the range of 35% to 60% with respect to an utility function proportional to the network throughput (S) divided by the average delay (D).

On the performance limits of slotted CSMA/CA in IEEE 802.15.4 for broadcast transmissions in wireless sensor networks

The IEEE 802.15.4 has been adopted as a communication protocol standard for Low-Rate Wireless Private Area Networks (LRWPANs). While it appears as a promising candidate solution for Wireless Sensor Networks (WSNs), its adequacy must be carefully evaluated. In this paper, we analyze the performance limits of the slotted CSMA/CA medium access control (MAC) mechanism in the beacon-enabled mode for broadcast transmissions in WSNs. The motivation for evaluating the beacon-enabled mode is due to its flexibility and potential for WSN applications as compared to the non-beacon enabled mode. Our analysis is based on an accurate simulation model of the slotted CSMA/CA mechanism on top of a realistic physical layer, with respect to the IEEE 802.15.4 standard specification. The performance of the slotted CSMA/CA is evaluated and analyzed for different network settings to understand the impact of the protocol attributes (superframe order, beacon order and backoff exponent), the number of nodes and the data frame size on the network performance, namely in terms of throughput (S), average delay (D) and probability of success (Ps). We also analytically evaluate the impact of the slotted CSMA/CA overheads on the saturation throughput. We introduce the concept of utility (U) as a combination of two or more metrics, to determine the best offered load range for an optimal behavior of the network. We show that the optimal network performance using slotted CSMA/CA occurs in the range of 35% to 60% with respect to an utility function proportional to the network throughput (S) divided by the average delay (D).

Run-time monitoring approach for the shark kernel

Typically common embedded systems are designed with high resource constraints. Static designs are often chosen to address very specific use cases. On contrast, a dynamic design must be used if the system must supply a real-time service where the input may contain factors of indeterminism. Thus, adding new functionality on these systems is often accomplished by higher development time, tests and costs, since new functionality push the system complexity and dynamics to a higher level. Usually, these systems have to adapt themselves to evolving requirements and changing service requests. In this perspective, run-time monitoring of the system behaviour becomes an important requirement, allowing to dynamically capturing the actual scheduling progress and resource utilization. For this to succeed, operating systems need to expose their internal behaviour and state, making it available to the external applications, usually using a run-time monitoring mechanism. However, such mechanism can impose a burden in the system itself if not wisely used. In this paper we explore this problem and propose a framework, which is intended to provide this run-time mechanism whilst achieving code separation, run-time efficiency and flexibility for the final developer.

A Java expression evaluator for nonlinear programming

Finding the optimal value for a problem is usual in many areas of knowledge where in many cases it is needed to solve Nonlinear Optimization Problems. For some of those problems it is not possible to determine the expression for its objective function and/or its constraints, they are the result of experimental procedures, might be non-smooth, among other reasons. To solve such problems it was implemented an API contained methods to solve both constrained and unconstrained problems. This API was developed to be used either locally on the computer where the application is being executed or remotely on a server. To obtain the maximum flexibility both from the programmers’ and users’ points of view, problems can be defined as a Java class (because this API was developed in Java) or as a simple text input that is sent to the API. For this last one to be possible it was also implemented on the API an expression evaluator. One of the drawbacks of this expression evaluator is that it is slower than the Java native code. In this paper it is presented a solution that combines both options: the problem can be expressed at run-time as a string of chars that are converted to Java code, compiled and loaded dynamically. To wide the target audience of the API, this new expression evaluator is also compatible with the AMPL format.

H.264/AVC backward compatible Bit-Depth scalable video coding

As high dynamic range video is gaining popularity, video coding solutions able to efficiently provide both low and high dynamic range video, notably with a single bitstream, are increasingly important. While simulcasting can provide both dynamic range videos at the cost of some compression efficiency penalty, bit-depth scalable video coding can provide a better trade-off between compression efficiency, adaptation flexibility and computational complexity. Considering the widespread use of H.264/AVC video, this paper proposes a H.264/AVC backward compatible bit-depth scalable video coding solution offering a low dynamic range base layer and two high dynamic range enhancement layers with different qualities, at low complexity. Experimental results show that the proposed solution has an acceptable rate-distortion performance penalty regarding the HDR H.264/AVC single-layer coding solution.

Periplasmic nitrate reductases: structural and spectroscopic studies

Dissertação apresentada para obtenção do grau de Doutor em Bioquímica, especialidade Bioquímica-Física, pela Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa

Políticas e modelos de gestão em unidades de fisioterapia: estratégias para a mudança

Mestrado em Intervenção Sócio-Organizacional na Saúde - Área de especialização: Políticas de Administração e Gestão de Serviços de Saúde

Optimal location of the workpiece in a PKM-based machining robotic cell

Most machining tasks require high accuracy and are carried out by dedicated machine-tools. On the other hand, traditional robots are flexible and easy to program, but they are rather inaccurate for certain tasks. Parallel kinematic robots could combine the accuracy and flexibility that are usually needed in machining operations. Achieving this goal requires proper design of the parallel robot. In this chapter, a multi-objective particle swarm optimization algorithm is used to optimize the structure of a parallel robot according to specific criteria. Afterwards, for a chosen optimal structure, the best location of the workpiece with respect to the robot, in a machining robotic cell, is analyzed based on the power consumed by the manipulator during the machining process.

A magnanimidade da teoria: interpretar a ética em teoria da literatura

Tese de doutoramento, Teoria da Literatura, Universidade de Lisboa, Faculdade de Letras, 2003

Optimal approximation of fractional derivatives through discrete-time fractions using genetic algorithms

This study addresses the optimization of rational fraction approximations for the discrete-time calculation of fractional derivatives. The article starts by analyzing the standard techniques based on Taylor series and Padé expansions. In a second phase the paper re-evaluates the problem in an optimization perspective by tacking advantage of the flexibility of the genetic algorithms.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Using NEXUS compliant debuggers for real time fault injection on microprocessors

As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.