Incremental learning from stream data

Recent years have witnessed an incredibly increasing interest in the topic of incremental learning. Unlike conventional machine learning situations, data flow targeted by incremental learning becomes available continuously over time. Accordingly, it is desirable to be able to abandon the traditional assumption of the availability of representative training data during the training period to develop decision boundaries. Under scenarios of continuous data flow, the challenge is how to transform the vast amount of stream raw data into information and knowledge representation, and accumulate experience over time to support future decision-making process. In this paper, we propose a general adaptive incremental learning framework named ADAIN that is capable of learning from continuous raw data, accumulating experience over time, and using such knowledge to improve future learning and prediction performance. Detailed system level architecture and design strategies are presented in this paper. Simulation results over several real-world data sets are used to validate the effectiveness of this method.

A Capabilities-Aware Framework for Using Computational Accelerators in Data-Intensive Computing

Multicore computational accelerators such as GPUs are now commodity components for highperformance computing at scale. While such accelerators have been studied in some detail as stand-alone computational engines, their integration in large-scale distributed systems raises new challenges and trade-offs. In this paper, we present an exploration of resource management alternatives for building asymmetric accelerator-based distributed systems. We present these alternatives in the context of a capabilities-aware framework for data-intensive computing, which uses an enhanced implementation of the MapReduce programming model for accelerator-based clusters, compared to the state of the art. The framework can transparently utilize heterogeneous accelerators for deriving high performance with low programming effort. Our work is the first to compare heterogeneous types of accelerators, GPUs and a Cell processors, in the same environment and the first to explore the trade-offs between compute-efficient and control-efficient accelerators on data-intensive systems. Our investigation shows that our framework scales well with the number of different compute nodes. Furthermore, it runs simultaneously on two different types of accelerators, successfully adapts to the resource capabilities, and performs 26.9% better on average than a static execution approach.

How resource quality differentially affects motivation and ability to fight in hermit crabs

Contesting animals typically gather information about the resource value and that information affects fight motivation. However, it is possible that particular resource characteristics alter the ability to fight independently of the motivation. Using hermit crabs, we investigate how the resource in terms of shell quality affects both motivation and ability to fight. These crabs fight for shells, but those shells have to be carried and may impose physiological costs that impede fight vigour. We find that the shell has different effects on motivation and ability. Potential attackers in very small shells were highly motivated to attack but, rather than having enhanced ability, unexpectedly quickly fatigued and subsequently were not more successful in the fights than were crabs in larger shells. We also examined whether defending crabs could gather information about the attacker's shell from the vigour of the attack. Defending crabs gave up quickly when a potential gain had been assessed, indicating that such information had been gathered. However, there was no indication that this could be owing to the activity of the attacker and the information is probably gathered via visual assessment of the shell.

Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

AND Logic Gates Based on Small Molecules with Chemical Inputs and Luminescence Output

AND logic gate behaviour can be recognized in chemical-responsive luminescence phenomena concerning small molecules. Though initial developments concerned separate and distinguishable chemical species as inputs, consideration of other types of input sets allows substantial expansion of the sub-field. Dissection of these molecular devices into modules, where possible, enables analysis of their logic behaviour according to supramolecular photochemical mechanisms.

Time dependence of the spatial coherence of the 23.6- and 23.2-nm radiation from the germanium soft-x-ray laser

The time dependence of the spatial coherence of the combined spectral lines at 23.2 and 23.6 nm from the Ge XXIII collisionally pumped soft-x-ray laser with a double-slab target is examined within a single nanosecond pulse by use of Young's interference fringes and a streak camera. High source intensity is linked with low spatial coherence and vice verse. Calculations of the source intensity, size, and position have also been made; these calculations refer to a single-slab source. Comparison between the observed and calculated intensities, and of the source sizes both calculated and derived from the Young's fringes by interpretation with a Gaussian model of source emission, show good agreement in general trends. (C) 1998 Optical Society of America [S0740-3224(98)01905-5].

A profile-based tool for finding pipeline parallelism in sequential programs

Traditional static analysis fails to auto-parallelize programs with a complex control and data flow. Furthermore, thread-level parallelism in such programs is often restricted to pipeline parallelism, which can be hard to discover by a programmer. In this paper we propose a tool that, based on profiling information, helps the programmer to discover parallelism. The programmer hand-picks the code transformations from among the proposed candidates which are then applied by automatic code transformation techniques.

This paper contributes to the literature by presenting a profiling tool for discovering thread-level parallelism. We track dependencies at the whole-data structure level rather than at the element level or byte level in order to limit the profiling overhead. We perform a thorough analysis of the needs and costs of this technique. Furthermore, we present and validate the belief that programs with complex control and data flow contain significant amounts of exploitable coarse-grain pipeline parallelism in the program’s outer loops. This observation validates our approach to whole-data structure dependencies. As state-of-the-art compilers focus on loops iterating over data structure members, this observation also explains why our approach finds coarse-grain pipeline parallelism in cases that have remained out of reach for state-of-the-art compilers. In cases where traditional compilation techniques do find parallelism, our approach allows to discover higher degrees of parallelism, allowing a 40% speedup over traditional compilation techniques. Moreover, we demonstrate real speedups on multiple hardware platforms.

Clustered indexing for branch predictors

As a result of resource limitations, state in branch predictors is frequently shared between uncorrelated branches. This interference can significantly limit prediction accuracy. In current predictor designs, the branches sharing prediction information are determined by their branch addresses and thus branch groups are arbitrarily chosen during compilation. This feasibility study explores a more analytic and systematic approach to classify branches into clusters with similar behavioral characteristics. We present several ways to incorporate this cluster information as an additional information source in branch predictors.

Standoff detection of weapons and contraband in the 100 GHz to 1 THz region

The techniques and technologies currently being investigated to detect weapons and contraband concealed on persons under clothing are reviewed. The basic phenomenology of the atmosphere and materials that must be understood in order to realize such a system are discussed. The component issues and architectural designs needed to realize systems are outlined. Some conclusions with respect to further technology developments are presented.

Free-space optoelectronic switching cores with MPLS for SANs over WDM ring networks

With increasing demands on storage devices in the modern communication environment, the storage area network (SAN) has evolved to provide a direct connection allowing these storage devices to be accessed efficiently. To optimize the performance of a SAN, a three-stage hybrid electronic/optical switching node architecture based on the concept of a MPLS label switching mechanism, aimed at serving as a multi-protocol label switching (MPLS) ingress label edge router (LER) for a SAN-enabled application, has been designed. New shutter-based free-space multi-channel optical switching cores are employed as the core switch fabric to solve the packet contention and switching path conflict problems. The system-level node architecture design constraints are evaluated through self-similar traffic sourced from real gigabit Ethernet network traces and storage systems. The extension performance of a SAN over a proposed WDM ring network, aimed at serving as an MPLS-enabled transport network, is also presented and demonstrated.