Claude Elwood Shannon e a symbolic analysis of relay and switching circuits: tornando o computador uma máquina semiótica.

O nome de Claude Elwood Shannon não é totalmente estranho aos pesquisadores de Comunicação Social. No entanto, parte de sua importância para a história da comunicação no século XX é pouco conhecida. Sua dissertação de mestrado e o artigo dela derivado (A Symbolic Analysis of Relay and Switching Circuits) foram essenciais para que o computador se tornasse uma máquina de comunicação e, conseqüentemente, penetrasse em nossa sociedade na forma como ocorre hoje. Este artigo revisa o primeiro grande trabalho de Shannon e explicita sua participação no contexto atual da comunicação.

Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Low cost BIST techniques for linear and non-linear analog circuits

With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter, multiple analog test points can be observed and specific analog test strategies can be enabled. As the digitizer is always connected to the analog test point, it is not necessary to include muxes and switches that would degrade the signal path. For RF analog circuits, this is specially useful, as the circuit impedance is fixed and the influence of the digitizer can be accounted for in the design phase. Thanks to the simplicity of the converter, it is able to reach higher frequencies, and enables the implementation of low cost RF test strategies. The digitizer has been applied successfully in the testing of both low frequency and RF analog circuits. Also, as testing is based on frequency-domain characteristics, nonlinear characteristics like intermodulation products can also be evaluated. Specifically, practical results were obtained for prototyped base band filters and a 100MHz mixer. The application of the converter for noise figure evaluation was also addressed, and experimental results for low frequency amplifiers using conventional opamps were obtained. The proposed method is able to enhance the testability of current mixed-signal designs, being suitable for the SoC environment used in many industrial products nowadays.

Comparação e validação de vários métodos de mapeamento cortical para o planeamento pré-cirúrgico por Imagem Funcional de Ressonância Magnética

Na análise funcional de imagens do cérebro podem utilizar-se diferentes métodos na identificação de zonas de activação. Tem havido uma evolução desde o método de correlação [19], para outros métodos [9] [14] até o método baseado no modelo linear generalizado que é mais comum ser utilizado hoje e que levou ao pacote de software SPM [15]. Deve-se principalmente à versatilidade que o método tem em realizar testes com diferentes objectivos. Têm sido publicados alguns estudos comparativos. Poucos têm sido quantitativos [20] e quando o são, o número de métodos testados é reduzido[22]. Há muitos estudos comparativos do ponto de vista da estatística envolvida (da matemática) mas que têm em geral apenas ns académicos. Um objectivo deste estudo é comparar os resultados obtidos por diferentes métodos. É de particular interesse averiguar o comportamento de cada método na fronteira do local de activação. As diferenças serão avaliadas numericamente para os seguintes métodos clássicos: t de Student, coeficiente de correlação e o modelo linear generalizado. Três novos métodos são também propostos - o método de picos de Fourier, o método de sobreposição e o método de amplitude. O segundo pode ser aplicado para o melhoramento dos métodos de t de Student, coe ciente de correlação e modelo linear generalizado. Ele pode no entanto, também manter-se como um método de análise independente. A influência exercida em cada método pelos parâmetros pertinentes é também medida. É adoptado um conjunto de dados clínicos que está amplamente estudado e documentado. Desta forma elimina-se a possibilidade dos resultados obtidos serem interpretados como sendo específicos do caso em estudo. Há situações em que a influência do método utilizado na identificação das áreas de activação de imagens funcionais do cérebro é crucial. Tal acontece, por exemplo, quando um tumor desenvolve-se perto de uma zona de activação responsável por uma função importante . Para o cirurgião tornase indispensável avaliar se existe alguma sobreposição. A escolha de um dos métodos disponíveis poderá ter infuência sobre a decisão final. Se o método escolhido for mais conservador, pode verificar-se sobreposição e eliminar-se a possibilidade de cirurgia. Porém, se o método for mais restritivo a decisão final pode ser favorável à cirurgia. Artigos recentes têm suportado a ideia de que a ressonância magnética funcional é de facto muito útil no processo de decisão pré-operatório [12].O segundo objectivo do estudo é então avaliar a sobreposição entre um volume de activação e o volume do tumor. Os programas informáticos de análise funcional disponíveis são variados em vários aspectos: na plataforma em que funcionam (macintosh, linux, windows ou outras), na linguagem em que foram desenvolvidos (e.g. c+motif, c+matlab, matlab, etc.) no tratamento inicial dos dados (antes da aplicação do método de análise), no formato das imagens e no(s) método(s) de análise escolhido(s). Este facto di culta qualquer tentativa de comparação. À partida esta poderá apenas ser qualitativa. Uma comparação quantitativa implicaria a necessidade de ocorrerem três factos: o utilizador tem acesso ao código do programa, sabe programar nas diferentes linguagens e tem licença de utilização de software comercial (e.g. matlab). Sendo assim foi decidido adoptar uma estratégia unificadora. Ou seja, criar um novo programa desenvolvido numa linguagem independente da plataforma, que não utilize software comercial e que permita aplicar (e comparar quantitativamente) diferentes métodos de análise funcional. A linguagem escolhida foi o JAVA. O programa desenvolvido no âmbito desta tese chama-se Cérebro.

Effects of Hormonal Supplementation on Nuclear Maturation and Cortical Granules Distribution of Canine Oocytes During Various Reproductive Stages

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Metamaterial inspired improved antennas and circuits

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Allocation of protective devices in distribution circuits using nonlinear programming models and genetic algorithms

The optimized allocation of protective devices in strategic points of the circuit improves the quality of the energy supply and the system reliability index. This paper presents a nonlinear integer programming (NLIP) model with binary variables, to deal with the problem of protective device allocation in the main feeder and all branches of an overhead distribution circuit, to improve the reliability index and to provide customers with service of high quality and reliability. The constraints considered in the problem take into account technical and economical limitations, such as coordination problems of serial protective devices, available equipment, the importance of the feeder and the circuit topology. The use of genetic algorithms (GAs) is proposed to solve this problem, using a binary representation that does (1) or does not (0) show allocation of protective devices (reclosers, sectionalizers and fuses) in predefined points of the circuit. Results are presented for a real circuit (134 busses), with the possibility of protective device allocation in 29 points. Also the ability of the algorithm in finding good solutions while improving significantly the indicators of reliability is shown. (C) 2003 Elsevier B.V. All rights reserved.

Vibration energy harvesting using piezoelectric transducer and non-controlled rectifiers circuits

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Iatrogenic cortical aneurysm post-craniotomy

Taking into account the number of craniotomies performed every day around the world, iatrogenic aneurysm post-craniotomy is extremely rare with only anecdotal cases reported in literature. We report an iatrogenic aneurysm affecting a cortical vessel which probably developed during dural closure of a conventional craniotomy. The aneurysm was discovered 6 months after surgery on a routine control angiography. The patient was successfully treated by trapping the parent vessel and excising the aneurysm. Histopathological findings were compatible with a true type of traumatic aneurysm. The possibility of this rare condition occurring highlights the risk of arterial injury during craniotomy.