Estudo do estado fundamental de aglomerados de silício via redes neurais

We introduce a global optimization method based on the cooperation between an Artificial Neural Net (ANN) and Genetic Algorithm (GA). We have used ANN to select the initial population for the GA. We have tested the new method to predict the ground-state geometry of silicon clusters. We have described the clusters as a piling of plane structures. We have trained three ANN architectures and compared their results with those of pure GA. ANN strongly reduces the total computational time. For Si10, it gained a factor of 5 in search speed. This method can be easily extended to other optimization problems.

Performance evaluation of MPEG-4 Video encoder on Adres

Actualment un típic embedded system (ex. telèfon mòbil) requereix alta qualitat per portar a terme tasques com codificar/descodificar a temps real; han de consumir poc energia per funcionar hores o dies utilitzant bateries lleugeres; han de ser el suficientment flexibles per integrar múltiples aplicacions i estàndards en un sol aparell; han de ser dissenyats i verificats en un període de temps curt tot i l’augment de la complexitat. Els dissenyadors lluiten contra aquestes adversitats, que demanen noves innovacions en arquitectures i metodologies de disseny. Coarse-grained reconfigurable architectures (CGRAs) estan emergent com a candidats potencials per superar totes aquestes dificultats. Diferents tipus d’arquitectures han estat presentades en els últims anys. L’alta granularitat redueix molt el retard, l’àrea, el consum i el temps de configuració comparant amb les FPGAs. D’altra banda, en comparació amb els tradicionals processadors coarse-grained programables, els alts recursos computacionals els permet d’assolir un alt nivell de paral•lelisme i eficiència. No obstant, els CGRAs existents no estant sent aplicats principalment per les grans dificultats en la programació per arquitectures complexes. ADRES és una nova CGRA dissenyada per I’Interuniversity Micro-Electronics Center (IMEC). Combina un processador very-long instruction word (VLIW) i un coarse-grained array per tenir dues opcions diferents en un mateix dispositiu físic. Entre els seus avantatges destaquen l’alta qualitat, poca redundància en les comunicacions i la facilitat de programació. Finalment ADRES és un patró enlloc d’una arquitectura concreta. Amb l’ajuda del compilador DRESC (Dynamically Reconfigurable Embedded System Compile), és possible trobar millors arquitectures o arquitectures específiques segons l’aplicació. Aquest treball presenta la implementació d’un codificador MPEG-4 per l’ADRES. Mostra l’evolució del codi per obtenir una bona implementació per una arquitectura donada. També es presenten les característiques principals d’ADRES i el seu compilador (DRESC). Els objectius són de reduir al màxim el nombre de cicles (temps) per implementar el codificador de MPEG-4 i veure les diferents dificultats de treballar en l’entorn ADRES. Els resultats mostren que els cícles es redueixen en un 67% comparant el codi inicial i final en el mode VLIW i un 84% comparant el codi inicial en VLIW i el final en mode CGA.

A química supramolecular de complexos pirazólicos

The purpose of this review is to describe the progress in the supramolecular chemistry of the pyrazolyl-based metal complexes. The text is written under the structural point of view, emphasizing the role of the covalent and non-covalent interactions in the rational construction of super and supramolecules.

Eletrodos modificados por hidróxido de níquel: um estudo de revisão sobre suas propriedades estruturais e eletroquímicas visando suas aplicações em eletrocatálise, eletrocromismo e baterias secundárias

The present review paper describes the main features of nickel hydroxide modified electrodes covering its structural and electrochemical behavior and the newest advances promoted by nanostructured architectures. Important aspects such as synthetic procedures and characterization techniques such as X-Ray diffraction, Raman and Infrared spectroscopy, Electronic Microscopy and many others are detailed herein. The most important aspect concerning nickel hydroxide is related to its great versatility covering different fields in electrochemical-based devices such as batteries, electrocatalytic systems and electrochromic electrodes, the fundamental issues of these devices are also commented. Finally, some of the newest advances achieved in each field by the incorporation of nanomaterials will be shown.

Romp as a versatile method for the obtention of differentiated polymeric materials

Ring Opening Metathesis Polymerization (ROMP) of cyclic olefins is a powerful transition metal-catalyzed reaction for syntheses of polymers and copolymers. The key feature of this reaction is the [2+2]-cycloaddition mechanism, with retention of the olefinic unsaturation in the polymer chain and occurrence of living polymerization. With the development of metal-carbene type catalysts for this process, many addressed polymeric materials have been successfully prepared to be employed in several fields of the science and technology. This review summarizes recent examples of syntheses of polymers with amphiphilic features such as block, graft, brush or star copolymers; as well syntheses of biomaterials, dendronized architectures, photoactive polymers, cross-linked or self-healing materials, and polymers from renewed supplies.

REDUÇÃO DE VARIÁVEIS DE ENTRADA DE REDES NEURAIS ARTIFICIAIS A PARTIR DE DADOS DE ANÁLISE DE COMPONENTES PRINCIPAIS NA MODELAGEM DE OXIGÊNIO DISSOLVIDO

The objective of this work is to demonstrate the efficient utilization of the Principal Components Analysis (PCA) as a method to pre-process the original multivariate data, that is rewrite in a new matrix with principal components sorted by it's accumulated variance. The Artificial Neural Network (ANN) with backpropagation algorithm is trained, using this pre-processed data set derived from the PCA method, representing 90.02% of accumulated variance of the original data, as input. The training goal is modeling Dissolved Oxygen using information of other physical and chemical parameters. The water samples used in the experiments are gathered from the Paraíba do Sul River in São Paulo State, Brazil. The smallest Mean Square Errors (MSE) is used to compare the results of the different architectures and choose the best. The utilization of this method allowed the reduction of more than 20% of the input data, which contributed directly for the shorting time and computational effort in the ANN training.

E-Business Intreoperability Frameworks for SMEs

Current e-business standards have been developed and used by large organizations to reduce clerical costs in business transactions by increased automation and higher level of business-to-business integration. Small and medium enterprises (SME's), however, cannot easily adopt these standards due to the SME's lacking the technical expertise and resources for implementing them. Still, large organizations increasingly require their business partners, most of which are SME's, to be able to interoperate by their chosen e-business standards. The research question for the study was, first, which of the existing e-business technologies are most SME-adoptable, and, second, how could those e-business technologies be made easier for SME's to implement. The study was conducted as a literature study that evaluated the available e-business frameworks and SME-oriented e-business architectures based on the implementation complexity and costs incurred for the SME adopter. The study found that only few e-business solutions are SMEadoptable. The technological approaches used in the solutions need to be improved on a number of areas, the most important of which is implementation complexity. The study revealed that this also applies to the special, SME-oriented e-business architectures, which are also still too difficult for SME's to implement. Based on these findings, a high-level e-business interoperability framework concept was proposed as the basis for future research to overcome the found implementation complexities for SME's.

Embedded controller system in crane application

The thesis studies possibility of using embedded controller in a crane application and furthermore defines requirements when designing such a controller. Basic crane control architectures are considered and compared. Then embedded controller product life cycle is described: considering such issues like microcontroller selection, software/hardware design and application development tools. Finally, available embedded controller is described and used for implementing crane control.

Julkishallinnon sähköisten palveluiden arkkitehtuurit

Sähköinen asiointi on yleistynyt viime vuosien aikana nopeasti. Toimivia julkishallinnon sähköisiä palveluita kehitetään jatkuvasti yhä uusiin tarkoituksiin. Tällä hetkellä sähköisten palveluiden tarjontaa leimaa hajanaisuus. Jokainen palveluita tarjoava organisaatio kehittää palveluita itsenäisesti, omalla tavallaan. Palveluiden kehittäminen asiakaslähtöisesti edellyttää palvelukokonaisuuksien suunnittelua arkkitehtuuritasolla. Yksittäisten sovellusten kehittämisen lisäksi on huomioitava näiden sovellusten toimivuus yhteen, osana suurempaa kokonaisuutta. Palvelukeskeisessä arkkitehtuurisuunnittelussa lähtökohta on se, että jokainen yksittäinen sovellus on itsessään palvelu, joka tuottaa määritelmänsä mukaisen tulosteen sellaisessa muodossa, jota muut sovellukset kykenevät ymmärtämään. Työn tuloksena havaittiin, että vaikka sähköiselle hallinnolle on kehitetty useita viitearkkitehtuureja, on käytännön työ palveluiden integroimiseksi vielä kesken. Yksittäisten palveluiden liittäminen suuremmiksi kokonaisuuksiksi vaatii määrätietoista arkkitehtuurisuunnittelua sekä kansallista suunnittelun koordinointia. Tiedon jakaminen organisaatiorajojen yli muodostaa joukon kysymyksiä, joihin ei ole vielä vastausta. Tietosuojaa ja yksityisyyttä ei voida uhrata sähköistä hallintoa suunniteltaessa.

Self-assembly of supermolecular species directed by hydrogen bonding and aromatic π-π stacking interactions

A new Cu(II) trimers, [Cu3(dcp)2(H2O)8]. 4DMF, with the ligand 3,5-pyrazoledicarboxylic acid monohydrate (H3dcp) has been prepared by solvent method. Its solid-state structure has been characterized by elemental analysis, thermal analysis (TGA and DSC), and single crystal X-ray diffraction. X-ray crystallographic studies reveal that this complex has extended 1-D,2-D and 3-D supramolecular architectures directed by weak interactions (hydrogen bond and aromatic π-π stacking interaction) leading to a sandwich solid-state structure.

Enterprise architecture – the foundation for a strategy

This artcle describes work done with enterprise architecture of the National Digital Library. The National Digital Library is an initiative of the Finnish Ministry of Education and Culture. Its purpose is to promote the availability of the digital information resources of archives, libraries and museums, and to develope the long-term preservation of digital cultural heritage materials. Enterprise architectures are a tool for strategic management and planning. An enterprise architecture also functions as an aid at a more practical level. It shows, for example, what kind of changes and improvements may be made in one system without overlap or conflict with other systems.

Exploring Adaptive Implementation of On-Chip Networks

As technology geometries have shrunk to the deep submicron regime, the communication delay and power consumption of global interconnections in high performance Multi- Processor Systems-on-Chip (MPSoCs) are becoming a major bottleneck. The Network-on- Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects and integration of large number of Processing Elements (PEs) on a chip. The choice of routing protocol and NoC structure can have a significant impact on performance and power consumption in on-chip networks. In addition, building a high performance, area and energy efficient on-chip network for multicore architectures requires a novel on-chip router allowing a larger network to be integrated on a single die with reduced power consumption. On top of that, network interfaces are employed to decouple computation resources from communication resources, to provide the synchronization between them, and to achieve backward compatibility with existing IP cores. Three adaptive routing algorithms are presented as a part of this thesis. The first presented routing protocol is a congestion-aware adaptive routing algorithm for 2D mesh NoCs which does not support multicast (one-to-many) traffic while the other two protocols are adaptive routing models supporting both unicast (one-to-one) and multicast traffic. A streamlined on-chip router architecture is also presented for avoiding congested areas in 2D mesh NoCs via employing efficient input and output selection. The output selection utilizes an adaptive routing algorithm based on the congestion condition of neighboring routers while the input selection allows packets to be serviced from each input port according to its congestion level. Moreover, in order to increase memory parallelism and bring compatibility with existing IP cores in network-based multiprocessor architectures, adaptive network interface architectures are presented to use multiple SDRAMs which can be accessed simultaneously. In addition, a smart memory controller is integrated in the adaptive network interface to improve the memory utilization and reduce both memory and network latencies. Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package density as compared to traditional 2D ICs. In addition, combining the benefits of 3D IC and NoC schemes provides a significant performance gain for 3D architectures. In recent years, inter-layer communication across multiple stacked layers (vertical channel) has attracted a lot of interest. In this thesis, a novel adaptive pipeline bus structure is proposed for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration. In addition, two mesh-based topologies for 3D architectures are also introduced to mitigate the inter-layer footprint and power dissipation on each layer with a small performance penalty.

Tactile-Proprioceptive Robotic Grasping

Robotic grasping has been studied increasingly for a few decades. While progress has been made in this field, robotic hands are still nowhere near the capability of human hands. However, in the past few years, the increase in computational power and the availability of commercial tactile sensors have made it easier to develop techniques that exploit the feedback from the hand itself, the sense of touch. The focus of this thesis lies in the use of this sense. The work described in this thesis focuses on robotic grasping from two different viewpoints: robotic systems and data-driven grasping. The robotic systems viewpoint describes a complete architecture for the act of grasping and, to a lesser extent, more general manipulation. Two central claims that the architecture was designed for are hardware independence and the use of sensors during grasping. These properties enables the use of multiple different robotic platforms within the architecture. Secondly, new data-driven methods are proposed that can be incorporated into the grasping process. The first of these methods is a novel way of learning grasp stability from the tactile and haptic feedback of the hand instead of analytically solving the stability from a set of known contacts between the hand and the object. By learning from the data directly, there is no need to know the properties of the hand, such as kinematics, enabling the method to be utilized with complex hands. The second novel method, probabilistic grasping, combines the fields of tactile exploration and grasp planning. By employing well-known statistical methods and pre-existing knowledge of an object, object properties, such as pose, can be inferred with related uncertainty. This uncertainty is utilized by a grasp planning process which plans for stable grasps under the inferred uncertainty.

Usable Privacy Preservation in Mobile Electronic Personality

Personalised ubiquitous services have rapidly proliferated due technological advancements in sensing, ubiquitous and mobile computing. Evolving societal trends, business and the economic potential of Personal Information (PI) have overlapped the service niches. At the same time, the societal thirst for more personalised services has increased and are met by soliciting deeper and more privacy invasive PI from customers. Consequentially, reinforcing traditional privacy challenges and unearthed new risks that render classical safeguards ine ective. The absence of solutions to criticise personalised ubiquitous services from privacy perspectives, aggravates the situation. This thesis presents a solution permitting users' PI, stored in their mobile terminals to be disclosed to services in privacy preserving manner for personalisation needs. The approach termed, Mobile Electronic Personality Version 2 (ME2.0), is compared to alternative mechanisms. Within ME2.0, PI handling vulnerabilities of ubiquitous services are identi ed and sensitised on their practices and privacy implications. Vulnerability where PI may leak through covert solicits, excessive acquisitions and legitimate data re-purposing to erode users privacy are also considered. In this thesis, the design, components, internal structures, architectures, scenarios and evaluations of ME2.0 are detailed. The design addresses implications and challenges leveraged by mobile terminals. ME2.0 components and internal structures discusses the functions related to how PI pieces are stored and handled by terminals and services. The architecture focusses on di erent components and their exchanges with services. Scenarios where ME2.0 is used are presented from di erent environment views, before evaluating for performance, privacy and usability.

Memristive Computing

Memristive computing refers to the utilization of the memristor, the fourth fundamental passive circuit element, in computational tasks. The existence of the memristor was theoretically predicted in 1971 by Leon O. Chua, but experimentally validated only in 2008 by HP Labs. A memristor is essentially a nonvolatile nanoscale programmable resistor — indeed, memory resistor — whose resistance, or memristance to be precise, is changed by applying a voltage across, or current through, the device. Memristive computing is a new area of research, and many of its fundamental questions still remain open. For example, it is yet unclear which applications would benefit the most from the inherent nonlinear dynamics of memristors. In any case, these dynamics should be exploited to allow memristors to perform computation in a natural way instead of attempting to emulate existing technologies such as CMOS logic. Examples of such methods of computation presented in this thesis are memristive stateful logic operations, memristive multiplication based on the translinear principle, and the exploitation of nonlinear dynamics to construct chaotic memristive circuits. This thesis considers memristive computing at various levels of abstraction. The first part of the thesis analyses the physical properties and the current-voltage behaviour of a single device. The middle part presents memristor programming methods, and describes microcircuits for logic and analog operations. The final chapters discuss memristive computing in largescale applications. In particular, cellular neural networks, and associative memory architectures are proposed as applications that significantly benefit from memristive implementation. The work presents several new results on memristor modeling and programming, memristive logic, analog arithmetic operations on memristors, and applications of memristors. The main conclusion of this thesis is that memristive computing will be advantageous in large-scale, highly parallel mixed-mode processing architectures. This can be justified by the following two arguments. First, since processing can be performed directly within memristive memory architectures, the required circuitry, processing time, and possibly also power consumption can be reduced compared to a conventional CMOS implementation. Second, intrachip communication can be naturally implemented by a memristive crossbar structure.