Electronic voting systems in undergraduate teaching

One of the major differences undergraduates experience during the transition to university is the style of teaching. In schools and colleges most students study key stage 5 subjects in relatively small informal groups where teacher–pupil interaction is encouraged and two-way feedback occurs through question and answer type delivery. On starting in HE students are amazed by the sizes of the classes. For even a relatively small chemistry department with an intake of 60-70 students, biologists, pharmacists, and other first year undergraduates requiring chemistry can boost numbers in the lecture hall to around 200 or higher. In many universities class sizes of 400 are not unusual for first year groups where efficiency is crucial. Clearly the personalised classroom-style delivery is not practical and it is a brave student who shows his ignorance by venturing to ask a question in front of such an audience. In these environments learning can be a very passive process, the lecture acts as a vehicle for the conveyance of information and our students are expected to reinforce their understanding by ‘self-study’, a term, the meaning of which, many struggle to understand. The use of electronic voting systems (EVS) in such situations can vastly change the students’ learning experience from a passive to a highly interactive process. This principle has already been demonstrated in Physics, most notably in the work of Bates and colleagues at Edinburgh.1 These small hand-held devices, similar to those which have become familiar through programmes such as ‘Who Wants to be a Millionaire’ can be used to provide instant feedback to students and teachers alike. Advances in technology now allow them to be used in a range of more sophisticated settings and comprehensive guides on use have been developed for even the most techno-phobic staff.

Convergence analysis of chip- and fractionally spaced LMS adaptive multiuser CDMA detectors

This paper analyzes the convergence behavior of the least mean square (LMS) filter when used in an adaptive code division multiple access (CDMA) detector consisting of a tapped delay line with adjustable tap weights. The sampling rate may be equal to or higher than the chip rate, and these correspond to chip-spaced (CS) and fractionally spaced (FS) detection, respectively. It is shown that CS and FS detectors with the same time-span exhibit identical convergence behavior if the baseband received signal is strictly bandlimited to half the chip rate. Even in the practical case when this condition is not met, deviations from this observation are imperceptible unless the initial tap-weight vector gives an extremely large mean squared error (MSE). This phenomenon is carefully explained with reference to the eigenvalues of the correlation matrix when the input signal is not perfectly bandlimited. The inadequacy of the eigenvalue spread of the tap-input correlation matrix as an indicator of the transient behavior and the influence of the initial tap weight vector on convergence speed are highlighted. Specifically, a initialization within the signal subspace or to the origin leads to very much faster convergence compared with initialization in the a noise subspace.

Methodology To model the energy and greenhouse gas emissions of electronic software distributions

A new electronic software distribution (ESD) life cycle analysis (LCA)methodology and model structure were constructed to calculate energy consumption and greenhouse gas (GHG) emissions. In order to counteract the use of high level, top-down modeling efforts, and to increase result accuracy, a focus upon device details and data routes was taken. In order to compare ESD to a relevant physical distribution alternative,physical model boundaries and variables were described. The methodology was compiled from the analysis and operational data of a major online store which provides ESD and physical distribution options. The ESD method included the calculation of power consumption of data center server and networking devices. An in-depth method to calculate server efficiency and utilization was also included to account for virtualization and server efficiency features. Internet transfer power consumption was analyzed taking into account the number of data hops and networking devices used. The power consumed by online browsing and downloading was also factored into the model. The embedded CO2e of server and networking devices was proportioned to each ESD process. Three U.K.-based ESD scenarios were analyzed using the model which revealed potential CO2e savings of 83% when ESD was used over physical distribution. Results also highlighted the importance of server efficiency and utilization methods.

Pocket data mining - big data on small devices

Owing to continuous advances in the computational power of handheld devices like smartphones and tablet computers, it has become possible to perform Big Data operations including modern data mining processes onboard these small devices. A decade of research has proved the feasibility of what has been termed as Mobile Data Mining, with a focus on one mobile device running data mining processes. However, it is not before 2010 until the authors of this book initiated the Pocket Data Mining (PDM) project exploiting the seamless communication among handheld devices performing data analysis tasks that were infeasible until recently. PDM is the process of collaboratively extracting knowledge from distributed data streams in a mobile computing environment. This book provides the reader with an in-depth treatment on this emerging area of research. Details of techniques used and thorough experimental studies are given. More importantly and exclusive to this book, the authors provide detailed practical guide on the deployment of PDM in the mobile environment. An important extension to the basic implementation of PDM dealing with concept drift is also reported. In the era of Big Data, potential applications of paramount importance offered by PDM in a variety of domains including security, business and telemedicine are discussed.

First-principles study of the inversion thermodynamics and electronic structure of FeM2X4 (thio)spinels (M = Cr, Mn, Co, Ni; X = O, S)

FeM2X4 spinels, where M is a transition metal and X is oxygen or sulfur, are candidate materials for spin filters, one of the key devices in spintronics. We present here a computational study of the inversion thermodynamics and the electronic structure of these (thio)spinels for M = Cr, Mn, Co, Ni, using calculations based on the density functional theory with on-site Hubbard corrections (DFT+U). The analysis of the configurational free energies shows that different behaviour is expected for the equilibrium cation distributions in these structures: FeCr2X4 and FeMn2S4 are fully normal, FeNi2X4 and FeCo2S4 are intermediate, and FeCo2O4 and FeMn2O4 are fully inverted. We have analyzed the role played by the size of the ions and by the crystal field stabilization effects in determining the equilibrium inversion degree. We also discuss how the electronic and magnetic structure of these spinels is modified by the degree of inversion, assuming that this could be varied from the equilibrium value. We have obtained electronic densities of states for the completely normal and completely inverse cation distribution of each compound. FeCr2X4, FeMn2X4, FeCo2O4 and FeNi2O4 are half-metals in the ferrimagnetic state when Fe is in tetrahedral positions. When M is filling the tetrahedral positions, the Cr-containing compounds and FeMn2O4 are half-metallic systems, while the Co and Ni spinels are insulators. The Co and Ni sulfide counterparts are metallic for any inversion degree together with the inverse FeMn2S4. Our calculations suggest that the spin filtering properties of the FeM2X4 (thio)spinels could be modified via the control of the cation distribution through variations in the synthesis conditions.

Electronic working length determination in primary teeth by Propex and Digital Signal Processing

The purpose of this study was to evaluate the accuracy of electronic apex locators Digital Signal Processing (DSP) and ProPex, for root canal length determination in primary teeth. Fifteen primary molars (a total of 34 root canals) were divided into two groups: Group I - without physiological resorption (n = 16); and Group II - with physiological resorption (n = 18). The length of each canal was measured by introducing a file until its tip was visible and then it was retracted 1 mm. For electronic measurement, the devices were set to 1 mm short of the apical resorption. The data were analysed statistically using the intraclass correlation coefficient (ICC). Results showed that the ICC was high for both electronic apex locators in all situations - with (ICC: DSP = 0.82 and Propex = 0.89) or without resorption (ICC: DSP = 0.92 and Propex = 0.90). Both apex locators were extremely accurate in determining the working length in primary teeth, both with or without physiological resorption.

Substitutional Impurities in PPV Crystals: An Intrinsic Donor-Acceptor System for High V(oc) Photovoltaic Devices

Defects are usually present in organic polymer films and are commonly invoked to explain the low efficiency obtained in organic-based optoelectronic devices. We propose that controlled insertion of substitutional impurities may, on the contrary, tune the optoelectronic properties of the underivatized organic material and, in the case studied here, maximize the efficiency of a solar cell. We investigate a specific oxygen-impurity substitution, the keto-defect -(CH(2)-C=O)- in underivatized crystalline poly(p-phenylenevinylene) (PPV), and its impact on the electronic structure of the bulk film, through a combined classical (force-field) and quantum mechanical (DFT) approach. We find defect states which suggest a spontaneous electron hole separation typical of a donor acceptor interface, optimal for photovoltaic devices. Furthermore, the inclusion of oxygen impurities does not introduce defect states in the gap and thus, contrary to standard donor-acceptor systems, should preserve the intrinsic high open circuit voltage (V(oc)) that may be extracted from PPV-based devices.

Application of abrupt cut-off models in the analysis of the capacitance spectra of conjugated polymer devices

In this paper, a detailed study of the capacitance spectra obtained from Au/doped-polyaniline/Al structures in the frequency domain (0.05 Hz-10 MHz), and at different temperatures (150-340 K) is carried out. The capacitance spectra behavior in semiconductors can be appropriately described by using abrupt cut-off models, since they assume that the electronic gap states that can follow the ac modulation have response times varying rapidly with a certain abscissa, which is dependent on both temperature and frequency. Two models based on the abrupt cut-off concept, formerly developed to describe inorganic semiconductor devices, have been used to analyze the capacitance spectra of devices based on doped polyaniline (PANI), which is a well-known polymeric semiconductor with innumerous potential technological applications. The application of these models allowed the determination of significant parameters, such as Debye length (approximate to 20 nm), position of bulk Fermi level (approximate to 320 meV) and associated density of states (approximate to 2x10(18) eV(-1) cm(-3)), width of the space charge region (approximate to 70 nm), built-in potential (approximate to 780 meV), and the gap states` distribution.

Low-Frequency Noise in Field-Effect Devices Functionalized With Dendrimer/Carbon-Nanotube Multilayers

Low-frequency noise in an electrolyte-insulator- semiconductor (EIS) structure functionalized with multilayers of polyamidoamine (PAMAM) dendrimer and single-walled carbon nanotubes (SWNT) is studied. The noise spectral density exhibits 1/f(gamma) dependence with the power factor of gamma approximate to 0.8 and gamma = 0.8-1.8 for the bare and functionalized EIS sensor, respectively. The gate-voltage noise spectral density is practically independent of the pH value of the solution and increases with increasing gate voltage or gate-leakage current. It has been revealed that functionalization of an EIS structure with a PAMAM/SWNTs multilayer leads to an essential reduction of the 1/f noise. To interpret the noise behavior in bare and functionalized EIS devices, a gate-current noise model for capacitive EIS structures based on an equivalent flatband-voltage fluctuation concept has been developed.

Structural-electronic aspects related to the near-infrared light emission of Fe-doped silicon films

The need of efficient (fast and low consumption) optoelectronic devices has always been the driving force behind the investigation of materials with new or improved properties. To be commercially attractive, however, these materials should be compatible with our current micro-electronics industry and/or telecommunications system. Silicon-based compounds, with their matured processing technology and natural abundance, partially comply with such requirements-as long as they emit light. Motivated by these issues, this work reports on the optical properties of amorphous Si films doped with Fe. The films were prepared by sputtering a Si+Fe target and were investigated by different spectroscopic techniques. According to the experimental results, both the Fe concentration and the thermal annealing of the samples induce changes in their atomic structure and optical-electronic properties. In fact, after thermal annealing at similar to 750 degrees C, the samples partially crystallize with the development of Si and/or beta-FeSi(2) crystallites. In such a case, certain samples present light emission at similar to 1500 nm that depends on the presence of beta-FeSi(2) crystallites and is very sensitive to the annealing conditions. The most likely reasons for the light emission (or absence of it) in the considered Fe-doped Si samples are presented and discussed in view of their main structural-electronic characteristics. (C) 2011 Elsevier Ltd. All rights reserved.

Use of copper and gold electrodes as sensitive elements for fabrication of an electronic tongue: Discrimination of wines and whiskies

A low-cost method is proposed to classify wine and whisky samples using a disposable voltammetric electronic tongue that was fabricated using gold and copper substrates and a pattern recognition technique (Principal Component Analysis). The proposed device was successfully used to discriminate between expensive and cheap whisky samples and to detect adulteration processes using only a copper electrode. For wines, the electronic tongue was composed of copper and gold working electrodes and was able to classify three different brands of wine and to make distinctions regarding the wine type, i.e., dry red, soft red, dry white and soft white brands. Crown Copyright (C) 2011 Published by Elsevier B.V. All rights reserved.

Electrical and optical properties of poly(2-dodecanoylsulfanyl-p-phenylenevnylene) and its application in electroluminescent devices

We describe the optical and electrical characterization of a poly(p-phenylenevinylene) derivative: poly(2-dodecanoylsulfanyl-p-phenylenevinylene) (12COS-PPV). The electrical characterization was carried out on devices with the FTO\PEDOT:PSS\12COS-PPV/Al structure. Positive charge carrier mobility mu(h) of similar to 1.0 x 10(-6) cm(2) V(-1) s(-1) and barrier height phi of similar to 0.1 eV for positive charge carrier injection at the PEDOT:PSS/12COS-PPV interface were obtained using a thermionic injection model. FTO\PEDOT:P55\12COS-PPV/Ca devices exhibited green-yellow electroluminescence with maximum emission at lambda = 540 nm.

System Integration of PV/T Collectors in Solar Cooling Systems

The demand for cooling and air-conditioning of building is increasingly ever growing. This increase is mostly due to population and economic growth in developing countries, and also desire for a higher quality of thermal comfort. Increase in the use of conventional cooling systems results in larger carbon footprint and more greenhouse gases considering their higher electricity consumption, and it occasionally creates peaks in electricity demand from power supply grid. Solar energy as a renewable energy source is an alternative to drive the cooling machines since the cooling load is generally high when solar radiation is high. This thesis examines the performance of PV/T solar collector manufactured by Solarus company in a solar cooling system for an office building in Dubai, New Delhi, Los Angeles and Cape Town. The study is carried out by analyzing climate data and the requirements for thermal comfort in office buildings. Cooling systems strongly depend on weather conditions and local climate. Cooling load of buildings depend on many parameters such as ambient temperature, indoor comfort temperature, solar gain to the building and internal gains including; number of occupant and electrical devices. The simulations were carried out by selecting a suitable thermally driven chiller and modeling it with PV/T solar collector in Polysun software. Fractional primary energy saving and solar fraction were introduced as key figures of the project to evaluate the performance of cooling system. Several parametric studies and simulations were determined according to PV/T aperture area and hot water storage tank volume. The fractional primary energy saving analysis revealed that thermally driven chillers, particularly adsorption chillers are not suitable to be utilizing in small size of solar cooling systems in hot and tropic climates such as Dubai and New Delhi. Adsorption chillers require more thermal energy to meet the cooling load in hot and dry climates. The adsorption chillers operate in their full capacity and in higher coefficient of performance when they run in a moderate climate since they can properly reject the exhaust heat. The simulation results also indicated that PV/T solar collector have higher efficiency in warmer climates, however it requires a larger size of PV/T collectors to supply the thermally driven chillers for providing cooling in hot climates. Therefore using an electrical chiller as backup gives much better results in terms of primary energy savings, since PV/T electrical production also can be used for backup electrical chiller in a net metering mechanism.

Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Reuse-based test planning for core-based systems-on-chip

Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.