Development and improvement of protection-system algorithms for ground-fault detection and location in synchronous machines

Uno de los defectos más frecuentes en los generadores síncronos son los defectos a tierra tanto en el devanado estatórico, como de excitación. Se produce un defecto cuando el aislamiento eléctrico entre las partes activas de cualquiera de estos devanados y tierra se reduce considerablemente o desaparece. La detección de los defectos a tierra en ambos devanados es un tema ampliamente estudiado a nivel industrial. Tras la detección y confirmación de la existencia del defecto, dicha falta debe ser localizada a lo largo del devanado para su reparación, para lo que habitualmente el rotor debe ser extraído del estator. Esta operación resulta especialmente compleja y cara. Además, el hecho de limitar la corriente de defecto en ambos devanados provoca que el defecto no sea localizable visualmente, pues apenas existe daño en el generador. Por ello, se deben aplicar técnicas muy laboriosas para localizar exactamente el defecto y poder así reparar el devanado. De cara a reducir el tiempo de reparación, y con ello el tiempo en que el generador esta fuera de servicio, cualquier información por parte del relé de protección acerca de la localización del defecto resultaría de gran utilidad. El principal objetivo de esta tesis doctoral ha sido el desarrollo de nuevos algoritmos que permitan la estimación de la localización de los defectos a tierra tanto en el devanado rotórico como estatórico de máquinas síncronas. Respecto al devanado de excitación, se ha presentado un nuevo método de localización de defectos a tierra para generadores con excitación estática. Este método permite incluso distinguir si el defecto se ha producido en el devanado de excitación, o en cualquiera de los componentes del sistema de excitación, esto es, transformador de excitación, conductores de alimentación del rectificador controlado, etc. En caso de defecto a tierra en del devanado rotórico, este método proporciona una estimación de su localización. Sin embargo, para poder obtener la localización del defecto, se precisa conocer el valor de resistencia de defecto. Por ello, en este trabajo se presenta además un nuevo método para la estimación de este parámetro de forma precisa. Finalmente, se presenta un nuevo método de detección de defectos a tierra, basado en el criterio direccional, que complementa el método de localización, permitiendo tener en cuenta la influencia de las capacidades a tierra del sistema. Estas capacidades resultan determinantes a la hora de localizar el defecto de forma adecuada. En relación con el devanado estatórico, en esta tesis doctoral se presenta un nuevo algoritmo de localización de defectos a tierra para generadores que dispongan de la protección de faltas a tierra basada en la inyección de baja frecuencia. Se ha propuesto un método general, que tiene en cuenta todos los parámetros del sistema, así como una versión simplificada del método para generadores con capacidades a tierra muy reducida, que podría resultar de fácil implementación en relés de protección comercial. Los algoritmos y métodos presentados se han validado mediante ensayos experimentales en un generador de laboratorio de 5 kVA, así como en un generador comercial de 106 MVA con resultados satisfactorios y prometedores. ABSTRACT One of the most common faults in synchronous generators is the ground fault in both the stator winding and the excitation winding. In case of fault, the insulation level between the active part of any of these windings and ground lowers considerably, or even disappears. The detection of ground faults in both windings is a very researched topic. The fault current is typically limited intentionally to a reduced level. This allows to detect easily the ground faults, and therefore to avoid damage in the generator. After the detection and confirmation of the existence of a ground fault, it should be located along the winding in order to repair of the machine. Then, the rotor has to be extracted, which is a very complex and expensive operation. Moreover, the fact of limiting the fault current makes that the insulation failure is not visually detectable, because there is no visible damage in the generator. Therefore, some laborious techniques have to apply to locate accurately the fault. In order to reduce the repair time, and therefore the time that the generator is out of service, any information about the approximate location of the fault would be very useful. The main objective of this doctoral thesis has been the development of new algorithms and methods to estimate the location of ground faults in the stator and in the rotor winding of synchronous generators. Regarding the excitation winding, a new location method of ground faults in excitation winding of synchronous machines with static excitation has been presented. This method allows even to detect if the fault is at the excitation winding, or in any other component of the excitation system: controlled rectifier, excitation transformer, etc. In case of ground fault in the rotor winding, this method provides an estimation of the fault location. However, in order to calculate the location, the value of fault resistance is necessary. Therefore, a new fault-resistance estimation algorithm is presented in this text. Finally, a new fault detection algorithm based on directional criterion is described to complement the fault location method. This algorithm takes into account the influence of the capacitance-to-ground of the system, which has a remarkable impact in the accuracy of the fault location. Regarding the stator winding, a new fault-location algorithm has been presented for stator winding of synchronous generators. This algorithm is applicable to generators with ground-fault protection based in low-frequency injection. A general algorithm, which takes every parameter of the system into account, has been presented. Moreover, a simplified version of the algorithm has been proposed for generators with especially low value of capacitance to ground. This simplified algorithm might be easily implementable in protective relays. The proposed methods and algorithms have been tested in a 5 kVA laboratory generator, as well as in a 106 MVA synchronous generator with satisfactory and promising results.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Bridge damage identification from moving load induced deflection based on wavelet transform and Lipschitz exponent

The wavelet transform and Lipschitz exponent perform well in detecting signal singularity.With the bridge crack damage modeled as rotational springs based on fracture mechanics, the deflection time history of the beam under the moving load is determined with a numerical method. The continuous wavelet transformation (CWT) is applied to the deflection of the beam to identify the location of the damage, and the Lipschitz exponent is used to evaluate the damage degree. The influence of different damage degrees,multiple damage, different sensor locations, load velocity and load magnitude are studied.Besides, the feasibility of this method is verified by a model experiment.

A regularised continuum damage model based on the mesoscopic scale for soft tissue

Material properties of soft fibrous tissues are highly conditioned by the hierarchical structure of this kind of composites. Collagen based tissues present, at decreasing length scales, a complex framework of fibres, fibrils, tropocollagen molecules and amino-acids. Understanding the mechanical behaviour at nano-scale level is critical to accurately incorporate this structural information in phenomenological damage models. In this work we derive a relationship between the mechanical and geometrical properties of the fibril constituents and the soft tissue material parameters at macroscopic scale. A Hodge–Petruska two-dimensional model has been used to describe the fibrils as staggered arrays of tropocollagen molecules. After a mechanical characterisation of each of the fibril components, two fibril failures modes have been defined related with two planes of weakness. A phenomenological continuous damage model with regularised softening was presented along with meso-structurally based definitions for its material parameters. Finally, numerical analysis at fibril, fibre and tissue levels are presented to show the capabilities of the model

Optical sensing of the fatigue damage state of CFRP under realistic aeronautical load sequences

We present an optical sensing methodology to estimate the fatigue damage state of structures made of carbon fiber reinforced polymer (CFRP), by measuring variations on the surface roughness. Variable amplitude loads (VAL), which represent realistic loads during aeronautical missions of fighter aircraft (FALSTAFF) have been applied to coupons until failure. Stiffness degradation and surface roughness variations have been measured during the life of the coupons obtaining a Pearson correlation of 0.75 between both variables. The data were compared with a previous study for Constant Amplitude Load (CAL) obtaining similar results. Conclusions suggest that the surface roughness measured in strategic zones is a useful technique for structural health monitoring of CFRP structures, and that it is independent of the type of load applied. Surface roughness can be measured in the field by optical techniques such as speckle, confocal perfilometers and interferometry, among others.

Application of the dynamic models to the detection of imperfections in plate Structures

This paper is part of a set of publications related with the development of mathematical models aimed to simulate the dynamic input and output of experimental nondestructive tests in order to detect structural imperfections. The structures to be considered are composed by steel plates of thin thickness. The imperfections in these cases are cracks and they can penetrate either a significant part of the plate thickness or be micro cracks or superficial imperfections. The first class of cracks is related with structural safety and the second one is more connected to the structural protection to the environment, particularly if protective paintings can be deteriorated. Two mathematical groups of models have been developed. The first group tries to locate the position and extension of the imperfection of the first class of imperfections, i.e. cracks and it is the object of the present paper. Bending Kirchoff thin plate models belong to this first group and they are used to this respect. The another group of models is dealt with membrane structures under the superficial Rayleigh waves excitation. With this group of models the micro cracks detection is intended. In the application of the first group of models to the detection of cracks, it has been observed that the differences between the natural frequencies of the non cracked and the cracked structures are very small. However, geometry and crack position can be identified quite accurately if this comparison is carried out between first derivatives (mode rotations) of the natural modes are used instead. Finally, in relation with the analysis of the superficial crack existence the use of Rayleigh waves is very promising. The geometry and the penetration of the micro crack can be detected very accurately. The mathematical and numerical treatment of the generation of these Rayleigh waves present and a numerical application has been shown.

A human Cds1-related kinase that functions downstream of ATM protein in the cellular response to DNA damage

Checkpoints maintain the order and fidelity of the eukaryotic cell cycle, and defects in checkpoints contribute to genetic instability and cancer. Much of our current understanding of checkpoints comes from genetic studies conducted in yeast. In the fission yeast Schizosaccharomyces pombe (Sp), SpRad3 is an essential component of both the DNA damage and DNA replication checkpoints. The SpChk1 and SpCds1 protein kinases function downstream of SpRad3. SpChk1 is an effector of the DNA damage checkpoint and, in the absence of SpCds1, serves an essential function in the DNA replication checkpoint. SpCds1 functions in the DNA replication checkpoint and in the S phase DNA damage checkpoint. Human homologs of both SpRad3 and SpChk1 but not SpCds1 have been identified. Here we report the identification of a human cDNA encoding a protein (designated HuCds1) that shares sequence, structural, and functional similarity to SpCds1. HuCds1 was modified by phosphorylation and activated in response to ionizing radiation. It was also modified in response to hydroxyurea treatment. Functional ATM protein was required for HuCds1 modification after ionizing radiation but not after hydroxyurea treatment. Like its fission yeast counterpart, human Cds1 phosphorylated Cdc25C to promote the binding of 14-3-3 proteins. These findings suggest that the checkpoint function of HuCds1 is conserved in yeast and mammals.

Evidence for a structural motif in toxins and interleukin-2 that may be responsible for binding to endothelial cells and initiating vascular leak syndrome

The dose-limiting toxicity of interleukin-2 (IL-2) and immunotoxin (IT) therapy in humans is vascular leak syndrome (VLS). VLS has a complex etiology involving damage to vascular endothelial cells (ECs), extravasation of fluids and proteins, interstitial edema, and organ failure. IL-2 and ITs prepared with the catalytic A chain of the plant toxin, ricin (RTA), and other toxins, damage human ECs in vitro and in vivo. Damage to ECs may initiate VLS; if this damage could be avoided without losing the efficacy of ITs or IL-2, larger doses could be administered. In this paper, we provide evidence that a three amino acid sequence motif, (x)D(y), in toxins and IL-2 damages ECs. Thus, when peptides from RTA or IL-2 containing this sequence motif are coupled to mouse IgG, they bind to and damage ECs both in vitro and, in the case of RTA, in vivo. In contrast, the same peptides with a deleted or mutated sequence do not. Furthermore, the peptide from RTA attached to mouse IgG can block the binding of intact RTA to ECs in vitro and vice versa. In addition, RTA, a fragment of Pseudomonas exotoxin A (PE38-lys), and fibronectin also block the binding of the mouse IgG-RTA peptide to ECs, suggesting that an (x)D(y) motif is exposed on all three molecules. Our results suggest that deletions or mutations in this sequence or the use of nondamaging blocking peptides may increase the therapeutic index of both IL-2, as well as ITs prepared with a variety of plant or bacterial toxins.

Induction of microsatellite instability by oxidative DNA damage

Instability of repetitive sequences, both in intronic sequences and within coding regions, has been demonstrated to be a hallmark of genomic instability in human cancer. Understanding how these mutational events arise may provide an opportunity for prevention or early intervention in cancer development. To study the source of this instability, we have identified a region of the β-lactamase gene that is tolerant to the insertion of fragments of exogenous DNA as large as 1,614 bp with minimal loss of enzyme activity, as determined by antibiotic resistance. Fragments inserted out-of-frame render Escherichia coli sensitive to antibiotic, and compensatory frameshift mutations that restore the reading frame of β-lactamase can be selected on the basis of antibiotic resistance. We have utilized this site to insert a synthetic microsatellite sequence within the β-lactamase gene and selected for mutations yielding frameshifts. This assay provides for detection of one frameshift mutation in a background of 106 wild-type sequences. Mismatch repair deficiency increased the observed frameshift frequency ≈300-fold. Exposure of plasmid containing microsatellite sequences to hydrogen peroxide resulted in frameshift mutations that were localized exclusively to the microsatellite sequences, whereas DNA damage by UV or N-methyl-N′-nitro-N-nitrosoguanidine did not result in enhanced mutagenesis. We postulate that in tumor cells, endogenous production of oxygen free radicals may be a major factor in promoting instability of microsatellite sequences. This β-lactamase assay may provide a sensitive methodology for the detection and quantitation of mutations associated with the development of cancer.

Detection and determination of oligonucleotide triplex formation-mediated transcription-coupled DNA repair in HeLa nuclear extracts

Transcription-coupled repair (TCR) plays an important role in removing DNA damage from actively transcribed genes. It has been speculated that TCR is the most important mechanism for repairing DNA damage in non-dividing cells such as neurons. Therefore, abnormal TCR may contribute to the development of many age-related and neurodegenerative diseases. However, the molecular mechanism of TCR is not well understood. Oligonucleotide DNA triplex formation provides an ideal system to dissect the molecular mechanism of TCR since triplexes can be formed in a sequence-specific manner to inhibit transcription of target genes. We have recently studied the molecular mechanism of triplex-forming oligonucleotide (TFO)-mediated TCR in HeLa nuclear extracts. Using plasmid constructs we demonstrate that the level of TFO-mediated DNA repair activity is directly correlated with the level of transcription of the plasmid in HeLa nuclear extracts. TFO-mediated DNA repair activity was further linked with transcription since the presence of rNTPs in the reaction was essential for AG30-mediated DNA repair activity in HeLa nuclear extracts. The involvement of individual components, including TFIID, TFIIH, RNA polymerase II and xeroderma pigmentosum group A (XPA), in the triplex-mediated TCR process was demonstrated in HeLa nuclear extracts using immunodepletion assays. Importantly, our studies also demonstrated that XPC, a component involved in global genome DNA repair, is involved in the AG30-mediated DNA repair process. The results obtained in this study provide an important new understanding of the molecular mechanisms involved in the TCR process in mammalian cells.

Treble clef finger—a functionally diverse zinc-binding structural motif

Detection of similarity is particularly difficult for small proteins and thus connections between many of them remain unnoticed. Structure and sequence analysis of several metal-binding proteins reveals unexpected similarities in structural domains classified as different protein folds in SCOP and suggests unification of seven folds that belong to two protein classes. The common motif, termed treble clef finger in this study, forms the protein structural core and is 25–45 residues long. The treble clef motif is assembled around the central zinc ion and consists of a zinc knuckle, loop, β-hairpin and an α-helix. The knuckle and the first turn of the helix each incorporate two zinc ligands. Treble clef domains constitute the core of many structures such as ribosomal proteins L24E and S14, RING fingers, protein kinase cysteine-rich domains, nuclear receptor-like fingers, LIM domains, phosphatidylinositol-3-phosphate-binding domains and His-Me finger endonucleases. The treble clef finger is a uniquely versatile motif adaptable for various functions. This small domain with a 25 residue structural core can accommodate eight different metal-binding sites and can have many types of functions from binding of nucleic acids, proteins and small molecules, to catalysis of phosphodiester bond hydrolysis. Treble clef motifs are frequently incorporated in larger structures or occur in doublets. Present analysis suggests that the treble clef motif defines a distinct structural fold found in proteins with diverse functional properties and forms one of the major zinc finger groups.

Selective binding of perfringolysin O derivative to cholesterol-rich membrane microdomains (rafts)

There is increasing evidence that sphingolipid- and cholesterol-rich microdomains (rafts) exist in the plasma membrane. Specific proteins assemble in these membrane domains and play a role in signal transduction and many other cellular events. Cholesterol depletion causes disassembly of the raft-associated proteins, suggesting an essential role of cholesterol in the structural maintenance and function of rafts. However, no tool has been available for the detection and monitoring of raft cholesterol in living cells. Here we show that a protease-nicked and biotinylated derivative (BCθ) of perfringolysin O (θ-toxin) binds selectively to cholesterol-rich microdomains of intact cells, the domains that fulfill the criteria of rafts. We fractionated the homogenates of nontreated and Triton X-100-treated platelets after incubation with BCθ on a sucrose gradient. BCθ was predominantly localized in the floating low-density fractions (FLDF) where cholesterol, sphingomyelin, and Src family kinases are enriched. Immunoelectron microscopy demonstrated that BCθ binds to a subpopulation of vesicles in FLDF. Depletion of 35% cholesterol from platelets with cyclodextrin, which accompanied 76% reduction in cholesterol from FLDF, almost completely abolished BCθ binding to FLDF. The staining patterns of BCθ and filipin in human epidermoid carcinoma A431 cells with and without cholesterol depletion suggest that BCθ binds to specific membrane domains on the cell surface, whereas filipin binding is indiscriminate to cell cholesterol. Furthermore, BCθ binding does not cause any damage to cell membranes, indicating that BCθ is a useful probe for the detection of membrane rafts in living cells.

Immunohistochemical detection of 4-hydroxynonenal protein adducts in Parkinson disease.

There is growing evidence that oxidative stress and mitochondrial respiratory failure with attendant decrease in energy output are implicated in nigral neuronal death in Parkinson disease (PD). It is not known, however, which cellular elements (neurons or glial cells) are major targets of oxygen-mediated damage. 4-Hydroxy-2-nonenal (HNE) was shown earlier to react with proteins to form stable adducts that can be used as markers of oxidative stress-induced cellular damage. We report here results of immunochemical studies using polyclonal antibodies directed against HNE-protein conjugates to label the site of oxidative damage in control subjects (ages 18-99 years) and seven patients that died of PD (ages 57-78 years). All the nigral melanized neurons in one of the midbrain sections were counted and classified into three groups according to the intensity of immunostaining for HNE-modified proteins--i.e., no staining, weak staining, and intensely positive staining. On average, 58% of nigral neurons were positively stained for HNE-modified proteins in PD; in contrast only 9% of nigral neurons were positive in the control subjects; the difference was statistically significant (Mann-Whitney U test; P < 0.01). In contrast to the substantia nigra, the oculomotor neurons in the same midbrain sections showed no or only weak staining for HNE-modified proteins in both PD and control subjects; young control subjects did not show any immunostaining; however, aged control subjects showed weak staining in the oculomotor nucleus, suggesting age-related accumulation of HNE-modified proteins in the neuron. Our results indicate the presence of oxidative stress within nigral neurons in PD, and this oxidative stress may contribute to nigral cell death.

Early p53 alterations in mouse skin carcinogenesis by UVB radiation: immunohistochemical detection of mutant p53 protein in clusters of preneoplastic epidermal cells.

High levels of the p53 protein are immunohistochemically detectable in a majority of human nonmelanoma skin cancers and UVB-induced murine skin tumors. These increased protein levels are often associated with mutations in the conserved domains of the p53 gene. To investigate the timing of the p53 alterations in the process of UVB carcinogenesis, we used a well defined murine model (SKH:HR1 hairless mice) in which the time that tumors appear is predictable from the UVB exposures. The mice were subjected to a series of daily UVB exposures, either for 17 days or for 30 days, which would cause skin tumors to appear around 80 or 30 weeks, respectively. In the epidermis of these mice, we detected clusters of cells showing a strong immunostaining of the p53 protein, as measured with the CM-5 polyclonal antiserum. This cannot be explained by transient accumulation of the normal p53 protein as a physiological response to UVB-induced DNA damage. In single exposure experiments the observed transient CM-5 immunoreactivity lasted for only 3 days and was not clustered, whereas these clusters were still detectable as long as 56 days after 17 days of UVB exposure. In addition, approximately 70% of these patches reacted with the mutant-specific monoclonal antibody PAb240, whereas transiently induced p53-positive cells did not. In line with indicative human data, these experimental results in the hairless mouse model unambiguously demonstrate that constitutive p53 alterations are causally related to chronic UVB exposure and that they are a very early event in the induction of skin cancer by UVB radiation.

Contextual visual localization: cascaded submap classification, optimized saliency detection, and fast view matching

In this paper, we present a novel coarse-to-fine visual localization approach: contextual visual localization. This approach relies on three elements: (i) a minimal-complexity classifier for performing fast coarse localization (submap classification); (ii) an optimized saliency detector which exploits the visual statistics of the submap; and (iii) a fast view-matching algorithm which filters initial matchings with a structural criterion. The latter algorithm yields fine localization. Our experiments show that these elements have been successfully integrated for solving the global localization problem. Context, that is, the awareness of being in a particular submap, is defined by a supervised classifier tuned for a minimal set of features. Visual context is exploited both for tuning (optimizing) the saliency detection process, and to select potential matching views in the visual database, close enough to the query view.