Self assembled and ordered group III nitride nanocolumnar structures for light emitting applications

El objetivo de este trabajo es un estudio profundo del crecimiento selectivo de nanoestructuras de InGaN por epitaxia de haces moleculares asistido por plasma, concentrandose en el potencial de estas estructuras como bloques constituyentes en LEDs de nueva generación. Varias aproximaciones al problema son discutidas; desde estructuras axiales InGaN/GaN, a estructuras core-shell, o nanoestructuras crecidas en sustratos con orientaciones menos convencionales (semi polar y no polar). La primera sección revisa los aspectos básicos del crecimiento auto-ensamblado de nanocolumnas de GaN en sustratos de Si(111). Su morfología y propiedades ópticas son comparadas con las de capas compactas de GaN sobre Si(111). En el caso de las columnas auto-ensambladas de InGaN sobre Si(111), se presentan resultados sobre el efecto de la temperatura de crecimiento en la incorporación de In. Por último, se discute la inclusión de nanodiscos de InGaN en las nanocolumnas de GaN. La segunda sección revisa los mecanismos básicos del crecimiento ordenado de nanoestructuras basadas en GaN, sobre templates de GaN/zafiro. Aumentando la relación III/V localmente, se observan cambios morfológicos; desde islas piramidales, a nanocolumnas de GaN terminadas en planos semipolares, y finalmente, a nanocolumnas finalizadas en planos c polares. Al crecer nanodiscos de InGaN insertados en las nanocolumnas de GaN, las diferentes morfologias mencionadas dan lugar a diferentes propiedades ópticas de los nanodiscos, debido al diferente carácter (semi polar o polar) de los planos cristalinos involucrados. La tercera sección recoge experimentos acerca de los efectos que la temperatura de crecimiento y la razón In/Ga tienen en la morfología y emisión de nanocolumnas ordenadas de InGaN crecidas sobre templates GaN/zafiro. En el rango de temperaturas entre 650 y 750 C, la incorporacion de In puede modificarse bien por la temperatura de crecimiento, o por la razón In/Ga. Controlar estos factores permite la optimización de la longitud de onda de emisión de las nanocolumnas de InGaN. En el caso particular de la generación de luz blanca, se han seguidos dos aproximaciones. En la primera, se obtiene emisión amarilla-blanca a temperatura ambiente de nanoestructuras donde la región de InGaN consiste en un gradiente de composiciones de In, que se ha obtenido a partir de un gradiente de temperatura durante el crecimiento. En la segunda, el apilamiento de segmentos emitiendo en azul, verde y rojo, consiguiendo la integración monolítica de estas estructuras en cada una de las nanocolumnas individuales, da lugar a emisores ordenados con un amplio espectro de emisión. En esta última aproximación, la forma espectral puede controlarse con la longitud (duración del crecimiento) de cada uno de los segmentos de InGaN. Más adelante, se presenta el crecimiento ordenado, por epitaxia de haces moleculares, de arrays de nanocolumnas que son diodos InGaN/GaN cada una de ellas, emitiendo en azul (441 nm), verde (502 nm) y amarillo (568 nm). La zona activa del dispositivo consiste en una sección de InGaN, de composición constante nominalmente y longitud entre 250 y 500 nm, y libre de defectos extendidos en contraste con capas compactas de InGaN de similares composiciones y espesores. Los espectros de electroluminiscencia muestran un muy pequeño desplazamiento al azul al aumentar la corriente inyectada (desplazamiento casi inexistente en el caso del dispositivo amarillo), y emisiones ligeramente más anchas que en el caso del estado del arte en pozos cuánticos de InGaN. A continuación, se presenta y discute el crecimiento ordenado de nanocolumnas de In(Ga)N/GaN en sustratos de Si(111). Nanocolumnas ordenadas emitiendo desde el ultravioleta (3.2 eV) al infrarrojo (0.78 eV) se crecieron sobre sustratos de Si(111) utilizando una capa compacta (“buffer”) de GaN. La morfología y eficiencia de emisión de las nanocolumnas emitiendo en el rango espectral verde pueden ser mejoradas ajustando las relaciones In/Ga y III/N, y una eficiencia cuántica interna del 30% se deriva de las medidas de fotoluminiscencia en nanocolumnas optimizadas. En la siguiente sección de este trabajo se presenta en detalle el mecanismo tras el crecimiento ordenado de nanocolumnas de InGaN/GaN emitiendo en el verde, y sus propiedades ópticas. Nanocolumnas de InGaN/GaN con secciones largas de InGaN (330-830 nm) se crecieron tanto en sustratos GaN/zafiro como GaN/Si(111). Se encuentra que la morfología y la distribución espacial del In dentro de las nanocolumnas dependen de las relaciones III/N e In/Ga locales en el frente de crecimiento de las nanocolumnas. La dispersión en el contenido de In entre diferentes nanocolumnas dentro de la misma muestra es despreciable, como indica las casi identicas formas espectrales de la catodoluminiscencia de una sola nanocolumna y del conjunto de ellas. Para las nanocolumnas de InGaN/GaN crecidas sobre GaN/Si(111) y emitiendo en el rango espectral verde, la eficiencia cuántica interna aumenta hasta el 30% al disminuir la temperatura de crecimiento y aumentar el nitrógeno activo. Este comportamiento se debe probablemente a la formación de estados altamente localizados, como indica la particular evolución de la energía de fotoluminiscencia con la temperatura (ausencia de “s-shape”) en muestras con una alta eficiencia cuántica interna. Por otro lado, no se ha encontrado la misma dependencia entre condiciones de crecimiento y efiencia cuántica interna en las nanoestructuras InGaN/GaN crecidas en GaN/zafiro, donde la máxima eficiencia encontrada ha sido de 3.7%. Como alternativa a las nanoestructuras axiales de InGaN/GaN, la sección 4 presenta resultados sobre el crecimiento y caracterización de estructuras core-shell de InGaN/GaN, re-crecidas sobre arrays de micropilares de GaN fabricados por ataque de un template GaN/zafiro (aproximación top-down). El crecimiento de InGaN/GaN es conformal, con componentes axiales y radiales en el crecimiento, que dan lugar a la estructuras core-shell con claras facetas hexagonales. El crecimiento radial (shell) se ve confirmado por medidas de catodoluminiscencia con resolución espacial efectuadas en un microscopio electrónico de barrido, asi como por medidas de microscopía de transmisión de electrones. Más adelante, el crecimiento de micro-pilares core-shell de InGaN se realizó en pilares GaN (cores) crecidos selectivamente por epitaxia de metal-orgánicos en fase vapor. Con el crecimiento de InGaN se forman estructuras core-shell con emisión alrededor de 3 eV. Medidas de catodoluminiscencia resuelta espacialmente indican un aumento en el contenido de indio del shell en dirección a la parte superior del pilar, que se manifiesta en un desplazamiento de la emisión de 3.2 eV en la parte inferior, a 3.0 eV en la parte superior del shell. Este desplazamiento está relacionado con variaciones locales de la razón III/V en las facetas laterales. Finalmente, se demuestra la fabricación de una estructura pin basada en estos pilares core-shell. Medidas de electroluminiscencia resuelta espacialmente, realizadas en pilares individuales, confirman que la electroluminiscencia proveniente del shell de InGaN (diodo lateral) está alrededor de 3.0 eV, mientras que la emisión desde la parte superior del pilar (diodo axial) está alrededor de 2.3 eV. Para finalizar, se presentan resultados sobre el crecimiento ordenado de GaN, con y sin inserciones de InGaN, en templates semi polares (GaN(11-22)/zafiro) y no polares (GaN(11-20)/zafiro). Tras el crecimiento ordenado, gran parte de los defectos presentes en los templates originales se ven reducidos, manifestándose en una gran mejora de las propiedades ópticas. En el caso de crecimiento selectivo sobre templates con orientación GaN(11-22), no polar, la formación de nanoestructuras con una particular morfología (baja relación entre crecimiento perpedicular frente a paralelo al plano) permite, a partir de la coalescencia de estas nanoestructuras, la fabricación de pseudo-templates no polares de GaN de alta calidad. ABSTRACT The aim of this work is to gain insight into the selective area growth of InGaN nanostructures by plasma assisted molecular beam epitaxy, focusing on their potential as building blocks for next generation LEDs. Several nanocolumn-based approaches such as standard axial InGaN/GaN structures, InGaN/GaN core-shell structures, or InGaN/GaN nanostructures grown on semi- and non-polar substrates are discussed. The first section reviews the basics of the self-assembled growth of GaN nanocolumns on Si(111). Morphology differences and optical properties are compared to those of GaN layer grown directly on Si(111). The effects of the growth temperature on the In incorporation in self-assembled InGaN nanocolumns grown on Si(111) is described. The second section reviews the basic growth mechanisms of selectively grown GaNbased nanostructures on c-plane GaN/sapphire templates. By increasing the local III/V ratio morphological changes from pyramidal islands, to GaN nanocolumns with top semi-polar planes, and further to GaN nanocolumns with top polar c-planes are observed. When growing InGaN nano-disks embedded into the GaN nanocolumns, the different morphologies mentioned lead to different optical properties, due to the semipolar and polar nature of the crystal planes involved. The third section reports on the effect of the growth temperature and In/Ga ratio on the morphology and light emission characteristics of ordered InGaN nanocolumns grown on c-plane GaN/sapphire templates. Within the growth temperature range of 650 to 750oC the In incorporation can be modified either by the growth temperature, or the In/Ga ratio. Control of these factors allows the optimization of the InGaN nanocolumns light emission wavelength. In order to achieve white light emission two approaches are used. First yellow-white light emission can be obtained at room temperature from nanostructures where the InGaN region is composition-graded by using temperature gradients during growth. In a second approach the stacking of red, green and blue emitting segments was used to achieve the monolithic integration of these structures in one single InGaN nanocolumn leading to ordered broad spectrum emitters. With this approach, the spectral shape can be controlled by changing the thickness of the respective InGaN segments. Furthermore the growth of ordered arrays of InGaN/GaN nanocolumnar light emitting diodes by molecular beam epitaxy, emitting in the blue (441 nm), green (502 nm), and yellow (568 nm) spectral range is reported. The device active region, consisting of a nanocolumnar InGaN section of nominally constant composition and 250 to 500 nm length, is free of extended defects, which is in strong contrast to InGaN layers (planar) of similar composition and thickness. Electroluminescence spectra show a very small blue shift with increasing current, (almost negligible in the yellow device) and line widths slightly broader than those of state-of-the-art InGaN quantum wells. Next the selective area growth of In(Ga)N/GaN nanocolumns on Si(111) substrates is discussed. Ordered In(Ga)N/GaN nanocolumns emitting from ultraviolet (3.2 eV) to infrared (0.78 eV) were then grown on top of GaN-buffered Si substrates. The morphology and the emission efficiency of the In(Ga)N/GaN nanocolumns emitting in the green could be substantially improved by tuning the In/Ga and total III/N ratios, where an estimated internal quantum efficiency of 30 % was derived from photoluminescence data. In the next section, this work presents a study on the selective area growth mechanisms of green-emitting InGaN/GaN nanocolumns and their optical properties. InGaN/GaN nanocolumns with long InGaN sections (330-830nm) were grown on GaN/sapphire and GaN-buffered Si(111). The nanocolumn’s morphology and spatial indium distribution is found to depend on the local group (III)/N and In/Ga ratios at the nanocolumn’s top. A negligible spread of the average indium incorporation among different nanostructures is found as indicated by similar shapes of the cathodoluminescence spectra taken from single nanocolumns and ensembles of nanocolumns. For InGaN/GaN nanocolumns grown on GaN-buffered Si(111), all emitting in the green spectral range, the internal quantum efficiency increases up to 30% when decreasing growth temperature and increasing active nitrogen. This behavior is likely due to the formation of highly localized states, as indicated by the absence of a complete s-shape behavior of the PL peak position with temperature (up to room temperature) in samples with high internal quantum efficiency. On the other hand, no dependence of the internal quantum efficiency on the growth conditions is found for InGaN/GaN nanostructures grown on GaN/sapphire, where the maximum achieved efficiency is 3.7%. As alternative to axial InGaN/GaN nanostructures, section 4 reports on the growth and characterization of InGaN/GaN core-shell structures on an ordered array of top-down patterned GaN microrods etched from a GaN/sapphire template. Growth of InGaN/GaN is conformal, with axial and radial growth components leading to core-shell structures with clear hexagonal facets. The radial InGaN growth (shell) is confirmed by spatially resolved cathodoluminescence performed in a scanning electron microscopy as well as in scanning transmission electron microscopy. Furthermore the growth of InGaN core-shell micro pillars using an ordered array of GaN cores grown by metal organic vapor phase epitaxy as a template is demonstrated. Upon InGaN overgrowth core-shell structures with emission at around 3.0 eV are formed. With spatially resolved cathodoluminescence, an increasing In content towards the pillar top is found to be present in the InGaN shell, as indicated by a shift of CL peak position from 3.2 eV at the shell bottom to 3.0 eV at the shell top. This shift is related to variations of the local III/V ratio at the side facets. Further, the successful fabrication of a core-shell pin diode structure is demonstrated. Spatially resolved electroluminescence measurements performed on individual micro LEDs, confirm emission from the InGaN shell (lateral diode) at around 3.0 eV, as well as from the pillar top facet (axial diode) at around 2.3 eV. Finally, this work reports on the selective area growth of GaN, with and without InGaN insertion, on semi-polar (11-22) and non-polar (11-20) templates. Upon SAG the high defect density present in the GaN templates is strongly reduced as indicated by TEM and a dramatic improvement of the optical properties. In case of SAG on non-polar (11-22) templates the formation of nanostructures with a low aspect ratio took place allowing for the fabrication of high-quality, non-polar GaN pseudo-templates by coalescence of the nanostructures.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Ubiquitously Expressed Dynamin-II Has a Higher Intrinsic GTPase Activity and a Greater Propensity for Self-assembly Than Neuronal Dynamin-I

To begin to understand mechanistic differences in endocytosis in neurons and nonneuronal cells, we have compared the biochemical properties of the ubiquitously expressed dynamin-II isoform with those of neuron-specific dynamin-I. Like dynamin-I, dynamin-II is specifically localized to and highly concentrated in coated pits on the plasma membrane and can assemble in vitro into rings and helical arrays. As expected, the two closely related isoforms share a similar mechanism for GTP hydrolysis: both are stimulated in vitro by self-assembly and by interaction with microtubules or the SH3 domain-containing protein, grb2. Deletion of the C-terminal proline/arginine-rich domain from either isoform abrogates self-assembly and assembly-dependent increases in GTP hydrolysis. However, dynamin-II exhibits a ∼threefold higher rate of intrinsic GTP hydrolysis and higher affinity for GTP than dynamin-I. Strikingly, the stimulated GTPase activity of dynamin-II can be >40-fold higher than dynamin-I, due principally to its greater propensity for self-assembly and the increased resistance of assembled dynamin-II to GTP-triggered disassembly. These results are consistent with the hypothesis that self-assembly is a major regulator of dynamin GTPase activity and that the intrinsic rate of GTP hydrolysis reflects a dynamic, GTP-dependent equilibrium of assembly and disassembly.

Medial prefrontal cortex and self-referential mental activity: Relation to a default mode of brain function

Medial prefrontal cortex (MPFC) is among those brain regions having the highest baseline metabolic activity at rest and one that exhibits decreases from this baseline across a wide variety of goal-directed behaviors in functional imaging studies. This high metabolic rate and this behavior suggest the existence of an organized mode of default brain function, elements of which may be either attenuated or enhanced. Extant data suggest that these MPFC regions may contribute to the neural instantiation of aspects of the multifaceted “self.” We explore this important concept by targeting and manipulating elements of MPFC default state activity. In this functional magnetic resonance imaging (fMRI) study, subjects made two judgments, one self-referential, the other not, in response to affectively normed pictures: pleasant vs. unpleasant (an internally cued condition, ICC) and indoors vs. outdoors (an externally cued condition, ECC). The ICC was preferentially associated with activity increases along the dorsal MPFC. These increases were accompanied by decreases in both active task conditions in ventral MPFC. These results support the view that dorsal and ventral MPFC are differentially influenced by attentiondemanding tasks and explicitly self-referential tasks. The presence of self-referential mental activity appears to be associated with increases from the baseline in dorsal MPFC. Reductions in ventral MPFC occurred consistent with the fact that attention-demanding tasks attenuate emotional processing. We posit that both self-referential mental activity and emotional processing represent elements of the default state as represented by activity in MPFC. We suggest that a useful way to explore the neurobiology of the self is to explore the nature of default state activity.

Molecular organization of histidine-tagged biomolecules at self-assembled lipid interfaces using a novel class of chelator lipids.

In molecular biology, the expression of fusion proteins is a very useful and well-established technique for the identification and one-step purification of gene products. Even a short fused sequence of five or six histidines enables proteins to bind to an immobilized metal ion chelate complex. By synthesis of a class of chelator lipids, we have transferred this approach to the concept of self-assembly. The specific interaction and lateral organization of a fluorescent fusion molecule containing a C-terminal oligohistidine sequence was studied by film balance techniques in combination with epifluorescence microscopy. Due to the phase behavior of the various lipid mixtures used, the chelator lipids can be laterally structured, generating two-dimensional arrays of histidine-tagged biomolecules. Because of the large variety of fusion proteins already available, this concept represents a powerful technique for orientation and organization of proteins at lipid interfaces with applications in biosensing, biofunctionalization of nanostructured interfaces, two-dimensional crystallization, and studies of lipid-anchored proteins.

Self-assembly of a charge-neutral molecular square

Complexation of cadmium(II) by the ditopic (bis-tridentate) thiocarbazone ligand 1,5-bis(6-methyl-2-pyridylmethylene) thiocarbonohydrazide, H2L1, results in the self-assembly of a charge-neutral 2 x 2 molecular grid, [Cd-4(L-1)(4)], comprising four metals and four ligands in an interlocked cyclic array. The solid-state structure of this tetramer has been established by X-ray crystallography and in solution by H-1 NMR spectroscopy. The presence of lower molecular weight oligomers was identified by both NMR and ESI-MS.

A self-similar array model of single-walled carbon nanotubes

To describe single-walled carbon nanotube (SWNT) arrays, we propose a self-similar array model. For isolated SWNT bundles, the self-similar array model is consistent with the classical triangular array model; for SWNT bundle arrays, it can present hierarchy structures and specify different array configurations. Based on this self-similar array model, we calculated the energetics of SWNT arrays, investigated the driving force for the formation of macroscopic SWNT arrays, and briefly discussed the hierarchy structures in real macroscopic SWNT arrays. (c) 2005 American Institute of Physics.

Generic Technique to Generate Large Branched DNA Complexes

The inherent self-recognition properties of DNA have led to its use as a scaffold for various nanotechnology self-assembly applications, with macromolecular complexes, metallic and semiconducting nanoparticles, proteins, inter alia, being assembled onto a designed DNA scaffold. Such structures may typically comprise a number of DNA molecules organized into macromolecules. Many studies have used synthetic methods to produce the constituent DNA molecules, but this typically constrains the molecules to be no longer than around 100 base pairs (30 nm). However, applications that require larger self-assembling DNA complexes, several tens of nanometers or more, need to be generated by other techniques. Here, we present a generic technique to generate large linear, branched, and/or circular DNA macromolecular complexes. The effectiveness of this technique is demonstrated here by the use of Lambda Bacteriophage DNA as a template to generate single- and double-branched DNA structures approximately 120 nm in size.

Mutations of beta-arrestin 2 that limit self-association also interfere with interactions with the beta2-adrenoceptor and the ERK1/2 MAPKs:implications for beta2-adrenoceptor signalling via the ERK1/2 MAPKs

FRET (fluorescence resonance energy transfer) and co-immunoprecipitation studies confirmed the capacity of beta-arrestin 2 to self-associate. Amino acids potentially involved in direct protein-protein interaction were identified via combinations of spot-immobilized peptide arrays and mapping of surface exposure. Among potential key amino acids, Lys(285), Arg(286) and Lys(295) are part of a continuous surface epitope located in the polar core between the N- and C-terminal domains. Introduction of K285A/R286A mutations into beta-arrestin 2-eCFP (where eCFP is enhanced cyan fluorescent protein) and beta-arrestin 2-eYFP (where eYFP is enhanced yellow fluorescent protein) constructs substantially reduced FRET, whereas introduction of a K295A mutation had a more limited effect. Neither of these mutants was able to promote beta2-adrenoceptor-mediated phosphorylation of the ERK1/2 (extracellular-signal-regulated kinase 1/2) MAPKs (mitogen-activated protein kinases). Both beta-arrestin 2 mutants displayed limited capacity to co-immunoprecipitate ERK1/2 and further spot-immobilized peptide arrays indicated each of Lys(285), Arg(286) and particularly Lys(295) to be important for this interaction. Direct interactions between beta-arrestin 2 and the beta2-adrenoceptor were also compromised by both K285A/R286A and K295A mutations of beta-arrestin 2. These were not non-specific effects linked to improper folding of beta-arrestin 2 as limited proteolysis was unable to distinguish the K285A/R286A or K295A mutants from wild-type beta-arrestin 2, and the interaction of beta-arrestin 2 with JNK3 (c-Jun N-terminal kinase 3) was unaffected by the K285A/R286A or L295A mutations. These results suggest that amino acids important for self-association of beta-arrestin 2 also play an important role in the interaction with both the beta2-adrenoceptor and the ERK1/2 MAPKs. Regulation of beta-arrestin 2 self-association may therefore control beta-arrestin 2-mediated beta2-adrenoceptor-ERK1/2 MAPK signalling.

An efficient route to highly organized, tunable macroporous-mesoporous alumina

(Figure Presented) Organized macroporous-mesoporous alumina can be obtained via a dual-templating approach. Monodispersed polystyrene beads promote macropore formation, while a P123 surfactant templating agent drives the formation of ordered hexagonal mesopores throughout the alumina framework. These well-defined pore networks coexist over a wide range of temperatures and macropore sizes. © 2009 American Chemical Society.

Silica promoted self-assembled mesoporous aluminas. Impact of the silica precursor on the structural, textural and acidic properties

This paper investigates the effect of silica addition on the structural, textural and acidic properties of an evaporation induced self-assembled (EISA) mesoporous alumina. Two silica addition protocols were applied while maintaining the EISA synthesis route. The first route is based on the addition of a Na-free colloidal silica suspension (Ludox®), and the second method consists of the co-hydrolysis of tetraethyl orthosilicate (TEOS) with aluminium tri-sec-butoxide, to favour a more intimate mixing of the Al- and Si-hydrolysed species. The properties of the so derived materials were compared to the SiO2-free counterpart. The SiO2 addition was always beneficial from a structural and textural standpoint. TEOS appears to have a truly promoting effect; the ordering, surface area and pore volume are all improved. For Ludox®, the enhancement comes from the formation of smaller pores by a densification of the structure. The crystallization of γ-alumina depends on the interaction between the Al- and Si-species in the mesophase. Ludox®-based materials achieved crystallization at 750 °C but the intimate mixing in the TEOS-based mesophases shows a suppression of the phase transformation by 50-100 °C, with respect to the SiO2-free counterpart. This reduces the textural features substantially. For all SiO2-modified materials, the enhancement in the surface area is not accompanied by a concomitant improvement of total acidity, and the formation of weak Lewis acid sites was promoted. These effects were ascribed to SiO2 migration to the surface that blocks part of the acidity.

Stabilization of self-assembled alumina mesophases

An efficient route to stabilize alumina mesophases derived from evaporation-induced self-assembly is reported after investigating various aspects in-depth: influence of the solvent (EtOH, s-BuOH, and t-BuOH) on the textural and structural properties of the mesophases based on aluminum tri-sec-butoxide (ATSB), synthesis reproducibility, role of nonvolatile acids, and the crystallization and thermal stability of the crystalline counterparts. Mesophase specific surface area and pore uniformity depend notably on the solvent; s-BuOH yields the highest surface area and pore uniformity. The optimal mesophase synthesis is reproducible with standard deviations in the textural parameters below 5%. The most pore-uniform mesophases from the three solvents were thermally activated at 1023 K to crystallize them into γ-alumina. The s-BuOH mesophase is remarkably thermally stable, retaining the mesoscopic wormhole order with 300 m2/g (0.45 cm3/g) and an increased acidic site density. These features are not obtained with EtOH or t-BuOH, where agglomerated γ-Al2O3 crystallites are formed with lower surface areas and broader pore size distributions. This was rationalized by the increase of the hydrolysis rate using EtOH and t-BuOH. t-BuOH dehydrates under the synthesis conditions or reacts with HCl, situations that increase the water concentration and rate of hydrolysis. It was found that EtOH exchanges rapidly, producing a highly reactive Al-ethoxide, thus enhancing the hydrolysis rate as well. Particle heterogeneity with random packing of fibrous and wormhole morphologies, attributed to the high hydrolysis rate, was observed for mesophases derived from both solvents. Such a low particle coordination favors coarsening with enlargement of the pore size distribution upon thermal treatment, explaining the lower thermal stability. Controlled hydrolysis and formation of low-polymerized Al species in s-BuOH are possibly responsible for the adequate assembly onto the surfactant. This was verified by the formation of a regular distribution of relatively size-uniform nanoparticles in the mesophase; high particle coordination prevents coarsening, favors densification, and maintains a relatively uniform pore size distribution upon thermal treatment. The acid removal in the evaporation is another key factor to promote network condensation in this route. © 2013 American Chemical Society.

Energy-efficient self -organization of wireless acoustic sensor networks for ground target tracking

With the developments in computing and communication technologies, wireless sensor networks have become popular in wide range of application areas such as health, military, environment and habitant monitoring. Moreover, wireless acoustic sensor networks have been widely used for target tracking applications due to their passive nature, reliability and low cost. Traditionally, acoustic sensor arrays built in linear, circular or other regular shapes are used for tracking acoustic sources. The maintaining of relative geometry of the acoustic sensors in the array is vital for accurate target tracking, which greatly reduces the flexibility of the sensor network. To overcome this limitation, we propose using only a single acoustic sensor at each sensor node. This design greatly improves the flexibility of the sensor network and makes it possible to deploy the sensor network in remote or hostile regions through air-drop or other stealth approaches. Acoustic arrays are capable of performing the target localization or generating the bearing estimations on their own. However, with only a single acoustic sensor, the sensor nodes will not be able to generate such measurements. Thus, self-organization of sensor nodes into virtual arrays to perform the target localization is essential. We developed an energy-efficient and distributed self-organization algorithm for target tracking using wireless acoustic sensor networks. The major error sources of the localization process were studied, and an energy-aware node selection criterion was developed to minimize the target localization errors. Using this node selection criterion, the self-organization algorithm selects a near-optimal localization sensor group to minimize the target tracking errors. In addition, a message passing protocol was developed to implement the self-organization algorithm in a distributed manner. In order to achieve extended sensor network lifetime, energy conservation was incorporated into the self-organization algorithm by incorporating a sleep-wakeup management mechanism with a novel cross layer adaptive wakeup probability adjustment scheme. The simulation results confirm that the developed self-organization algorithm provides satisfactory target tracking performance. Moreover, the energy saving analysis confirms the effectiveness of the cross layer power management scheme in achieving extended sensor network lifetime without degrading the target tracking performance.

Energy-Efficient Self-Organization of Wireless Acoustic Sensor Networks for Ground Target Tracking

With the developments in computing and communication technologies, wireless sensor networks have become popular in wide range of application areas such as health, military, environment and habitant monitoring. Moreover, wireless acoustic sensor networks have been widely used for target tracking applications due to their passive nature, reliability and low cost. Traditionally, acoustic sensor arrays built in linear, circular or other regular shapes are used for tracking acoustic sources. The maintaining of relative geometry of the acoustic sensors in the array is vital for accurate target tracking, which greatly reduces the flexibility of the sensor network. To overcome this limitation, we propose using only a single acoustic sensor at each sensor node. This design greatly improves the flexibility of the sensor network and makes it possible to deploy the sensor network in remote or hostile regions through air-drop or other stealth approaches. Acoustic arrays are capable of performing the target localization or generating the bearing estimations on their own. However, with only a single acoustic sensor, the sensor nodes will not be able to generate such measurements. Thus, self-organization of sensor nodes into virtual arrays to perform the target localization is essential. We developed an energy-efficient and distributed self-organization algorithm for target tracking using wireless acoustic sensor networks. The major error sources of the localization process were studied, and an energy-aware node selection criterion was developed to minimize the target localization errors. Using this node selection criterion, the self-organization algorithm selects a near-optimal localization sensor group to minimize the target tracking errors. In addition, a message passing protocol was developed to implement the self-organization algorithm in a distributed manner. In order to achieve extended sensor network lifetime, energy conservation was incorporated into the self-organization algorithm by incorporating a sleep-wakeup management mechanism with a novel cross layer adaptive wakeup probability adjustment scheme. The simulation results confirm that the developed self-organization algorithm provides satisfactory target tracking performance. Moreover, the energy saving analysis confirms the effectiveness of the cross layer power management scheme in achieving extended sensor network lifetime without degrading the target tracking performance.

Intercomparison of soil pore water extraction methods for stable isotope analysis

Peer reviewed