Gain-of-function mutation S422L in the KCNJ8-encoded cardiac K(ATP) channel Kir6.1 as a pathogenic substrate for J-wave syndromes.

BACKGROUND J-wave syndromes have emerged conceptually to encompass the pleiotropic expression of J-point abnormalities including Brugada syndrome (BrS) and early repolarization syndrome (ERS). KCNJ8, which encodes the cardiac K(ATP) Kir6.1 channel, recently has been implicated in ERS following identification of the functionally uncharacterized missense mutation S422L. OBJECTIVE The purpose of this study was to further explore KCNJ8 as a novel susceptibility gene for J-wave syndromes. METHODS Using polymerase chain reaction, denaturing high-performance liquid chromatography, and direct DNA sequencing, comprehensive open reading frame/splice site mutational analysis of KCNJ8 was performed in 101 unrelated patients with J-wave syndromes, including 87 with BrS and 14 with ERS. Six hundred healthy individuals were examined to assess the allelic frequency for all variants detected. KCNJ8 mutation(s) was engineered by site-directed mutagenesis and coexpressed heterologously with SUR2A in COS-1 cells. Ion currents were recorded using whole-cell configuration of the patch-clamp technique. RESULTS One BrS case and one ERS case hosted the identical missense mutation S422L, which was reported previously. KCNJ8-S422L involves a highly conserved residue and was absent in 1,200 reference alleles. Both cases were negative for mutations in all known BrS and ERS susceptibility genes. K(ATP) current of the Kir6.1-S422L mutation was increased significantly over the voltage range from 0 to 40 mV compared to Kir6.1-WT channels (n = 16-21; P <.05). CONCLUSION These findings further implicate KCNJ8 as a novel J-wave syndrome susceptibility gene and a marked gain of function in the cardiac K(ATP) Kir6.1 channel secondary to KCNJ8-S422L as a novel pathogenic mechanism for the phenotypic expression of both BrS and ERS.

The RYR2-encoded ryanodine receptor/calcium release channel in patients diagnosed previously with either catecholaminergic polymorphic ventricular tachycardia or genotype negative, exercise-induced long QT syndrome: a comprehensive open reading frame mutational analysis.

OBJECTIVES This study was undertaken to determine the spectrum and prevalence of mutations in the RYR2-encoded cardiac ryanodine receptor in cases with exertional syncope and normal corrected QT interval (QTc). BACKGROUND Mutations in RYR2 cause type 1 catecholaminergic polymorphic ventricular tachycardia (CPVT1), a cardiac channelopathy with increased propensity for lethal ventricular dysrhythmias. Most RYR2 mutational analyses target 3 canonical domains encoded by <40% of the translated exons. The extent of CPVT1-associated mutations localizing outside of these domains remains unknown as RYR2 has not been examined comprehensively in most patient cohorts. METHODS Mutational analysis of all RYR2 exons was performed using polymerase chain reaction, high-performance liquid chromatography, and deoxyribonucleic acid sequencing on 155 unrelated patients (49% females, 96% Caucasian, age at diagnosis 20 +/- 15 years, mean QTc 428 +/- 29 ms), with either clinical diagnosis of CPVT (n = 110) or an initial diagnosis of exercise-induced long QT syndrome but with QTc <480 ms and a subsequent negative long QT syndrome genetic test (n = 45). RESULTS Sixty-three (34 novel) possible CPVT1-associated mutations, absent in 400 reference alleles, were detected in 73 unrelated patients (47%). Thirteen new mutation-containing exons were identified. Two-thirds of the CPVT1-positive patients had mutations that localized to 1 of 16 exons. CONCLUSIONS Possible CPVT1 mutations in RYR2 were identified in nearly one-half of this cohort; 45 of the 105 translated exons are now known to host possible mutations. Considering that approximately 65% of CPVT1-positive cases would be discovered by selective analysis of 16 exons, a tiered targeting strategy for CPVT genetic testing should be considered.

SCN4B-encoded sodium channel beta4 subunit in congenital long-QT syndrome.

BACKGROUND Congenital long-QT syndrome (LQTS) is potentially lethal secondary to malignant ventricular arrhythmias and is caused predominantly by mutations in genes that encode cardiac ion channels. Nearly 25% of patients remain without a genetic diagnosis, and genes that encode cardiac channel regulatory proteins represent attractive candidates. Voltage-gated sodium channels have a pore-forming alpha-subunit associated with 1 or more auxiliary beta-subunits. Four different beta-subunits have been described. All are detectable in cardiac tissue, but none have yet been linked to any heritable arrhythmia syndrome. METHODS AND RESULTS We present a case of a 21-month-old Mexican-mestizo female with intermittent 2:1 atrioventricular block and a corrected QT interval of 712 ms. Comprehensive open reading frame/splice mutational analysis of the 9 established LQTS-susceptibility genes proved negative, and complete mutational analysis of the 4 Na(vbeta)-subunits revealed a L179F (C535T) missense mutation in SCN4B that cosegregated properly throughout a 3-generation pedigree and was absent in 800 reference alleles. After this discovery, SCN4B was analyzed in 262 genotype-negative LQTS patients (96% white), but no further mutations were found. L179F was engineered by site-directed mutagenesis and heterologously expressed in HEK293 cells that contained the stably expressed SCN5A-encoded sodium channel alpha-subunit (hNa(V)1.5). Compared with the wild-type, L179F-beta4 caused an 8-fold (compared with SCN5A alone) and 3-fold (compared with SCN5A + WT-beta4) increase in late sodium current consistent with the molecular/electrophysiological phenotype previously shown for LQTS-associated mutations. CONCLUSIONS We provide the seminal report of SCN4B-encoded Na(vbeta)4 as a novel LQT3-susceptibility gene.

The electrophysiology of glomerular mesangial cells

Glomerular mesangial cells (MC) are renal vascular cells that regulate the surface area of glomerular capillaries and thus, partly control glomerular filtration rate. Clarification of the signal transduction pathways and ionic mechanisms modulating MC tone are critical to understanding the physiology and pathophysiology of these cells, and the integrative role these cells play in fluid and electrolyte homeostasis. The patch clamp technique and an assay of cell concentration were used to electrophysiologically and pharmacologically analyze the ion channels of the plasmalemmal of human glomerular MC maintained in tissue culture. Moreover, the signal transduction pathways modulating channels involved in relaxation were investigated. Three distinct K$\sp+$-selective channels were identified: two low conductance channels (9 and 65pS) maintained MC at rest, while a larger conductance (206pS) K$\sp+$ channel was quiescent at rest. This latter channel was pharmacologically and biophysically similar to the large, Ca$\sp{2+}$-activated K$\sp+$ channel (BK$\rm\sb{Ca}$) identified in smooth muscle. BK$\rm\sb{Ca}$ played an essential role in relaxation of MC. In cell-attached patches, the open probability (P$\rm\sb{o}$) of BK$\rm\sb{Ca}$ increased from a basal level of $<$0.05 to 0.22 in response to AII (100nM)-induced mobilization of cytosolic Ca$\sp{2+}$. Activation in response to contractile signals (membrane depolarization and Ca$\sp{2+}$ mobilization) suggests that BK$\rm\sb{Ca}$ acts as a low gain feedback regulator of contraction. Atrial natriuretic factor (ANF; 1.0$\mu$M) and nitroprusside (NP; 0.1mM), via the second messenger, cGMP, increase the feedback gain of BK$\rm\sb{Ca}$. In cell-attached patches bathed with physiological saline, these agents transiently activated BK$\rm\sb{Ca}$ from a basal $\rm P\sb{o}<0.05$ to peak responses near 0.50. As membrane potential hyperpolarizes towards $\rm E\sb{K}$ (2-3 minutes), BK$\rm\sb{Ca}$ inactivates. Upon depolarizing V$\rm\sb{m}$ with 140 mM KCl, db-cGMP (10$\mu$M) activated BK$\rm\sb{Ca}$ to a sustained P$\rm\sb{o}$ = 0.51. Addition of AII in the presence of cGMP further increased P$\rm\sb{o}$ to 0.82. Activation of BK$\rm\sb{Ca}$ by cGMP occured via an endogenous cGMP-dependent protein kinase (PKG): in excised, inside-out patches, PKG in the presence of Mg-ATP (0.1mM) and cGMP increased P$\rm\sb{o}$ from 0.07 to 0.39. In contrast, neither PKC nor PKA influenced BK$\rm\sb{Ca}$. Endogenous okadaic acid-sensitive protein phosphatase suppressed BK$\rm\sb{Ca}$ activity. Binning the change in P$\rm\sb{o}\ (\Delta P\sb{o}$) of BK$\rm\sb{Ca}$ in response to PKG (n = 69) established two distinct populations of channels: one that responded ($\cong$67%, $\rm\Delta P\sb{o} = 0.45 \pm 0.03$) and one that was unresponsive ($\Delta\rm P\sb{o} = 0.00 \pm 0.01$) to PKG. Activation of BK$\rm\sb{Ca}$ by PKG resulted from a decrease in the Ca$\sp{2+}$- and voltage-activation thresholds independent of sensitivities. In conclusion, mesangial BK$\rm\sb{Ca}$ channels sense both electrical and chemical signals of contraction and act as feedback regulators by repolarizing the plasma membrane. ANF and NO, via cGMP, stimulate endogenous PKG, which subsequently decreases the activation threshold of BK$\rm\sb{Ca}$ to increase the gain of this feedback regulatory signal. ^

The polarized distribution of poly(A+)-mRNA-induced functional ion channels in the Xenopus oocyte plasma membrane is prevented by anticytoskeletal drugs

Foreign mRNA was expressed in Xenopus laevis oocytes. Newly expressed ion currents localized in defined plasma membrane areas were measured using the two-electrode voltage clamp technique in combination with a specially designed chamber, that exposed only part of the surface on the oocytes to channel agonists or inhibitors. Newly expressed currents were found to be unequally distributed in the surface membrane of the oocyte. This asymmetry was most pronounced during the early phase of expression, when channels could almost exclusively be detected in the animal hemisphere of the oocyte. 4 d after injection of the mRNA, or later, channels could be found at a threefold higher density at the animal than at the vegetal pole area. The pattern of distribution was observed to be similar with various ion channels expressed from crude tissue mRNA and from cRNAs coding for rat GABAA receptor channel subunits. Electron microscopical analysis revealed very similar microvilli patterns at both oocyte pole areas. Thus, the asymmetric current distribution is not due to asymmetric surface structure. Upon incubation during the expression period in either colchicine or cytochalasin D, the current density was found to be equal in both pole areas. The inactive control substance beta-lumicolchicine had no effect on the asymmetry of distribution. Colchicine was without effect on the amplitude of the expressed whole cell current. Our measurements reveal a pathway for plasma membrane protein expression endogenous to the Xenopus oocyte, that may contribute to the formation and maintenance of polarity of this highly organized cell.

Glycosylation of TRPM4 and TRPM5 channels: molecular determinants and functional aspects

The transient receptor potential channel, TRPM4, and its closest homolog, TRPM5, are non-selective cation channels that are activated by an increase in intracellular calcium. They are expressed in many cell types, including neurons and myocytes. Although the electrophysiological and pharmacological properties of these two channels have been previously studied, less is known about their regulation, in particular their post-translational modifications. We, and others, have reported that wild-type (WT) TRPM4 channels expressed in HEK293 cells, migrated on SDS-PAGE gel as doublets, similar to other ion channels and membrane proteins. In the present study, we provide evidence that TRPM4 and TRPM5 are each N-linked glycosylated at a unique residue, Asn(992) and Asn(932), respectively. N-linked glycosylated TRPM4 is also found in native cardiac cells. Biochemical experiments using HEK293 cells over-expressing WT TRPM4/5 or N992Q/N932Q mutants demonstrated that the abolishment of N-linked glycosylation did not alter the number of channels at the plasma membrane. In parallel, electrophysiological experiments demonstrated a decrease in the current density of both mutant channels, as compared to their respective controls, either due to the Asn to Gln mutations themselves or abolition of glycosylation. To discriminate between these possibilities, HEK293 cells expressing TRPM4 WT were treated with tunicamycin, an inhibitor of glycosylation. In contrast to N-glycosylation signal abolishment by mutagenesis, tunicamycin treatment led to an increase in the TRPM4-mediated current. Altogether, these results demonstrate that TRPM4 and TRPM5 are both N-linked glycosylated at a unique site and also suggest that TRPM4/5 glycosylation seems not to be involved in channel trafficking, but mainly in their functional regulation.

Study of Heavy-ion Induced Fission for Heavy Element Synthesis

Fission fragment mass distributions were measured in heavy-ion induced fission of 238U. The mass distributions changed drastically with incident energy. The results are explained by a change of the ratio between fusion and quasifission with nuclear orientation. A calculation based on a fluctuation dissipation model reproduced the mass distributions and their incident energy dependence. Fusion probability was determined in the analysis. Evaporation residue cross sections were calculated with a statistical model for the reactions of 30Si+238U and 34S+238U using the obtained fusion probability in the entrance channel. The results agree with the measured cross sections of 263,264Sg and 267,268Hs, produced by 30Si+238U and 34S+238U, respectively. It is also suggested that sub-barrier energies can be used for heavy element synthesis.

Optimization of TRPV6 Calcium Channel Inhibitors Using a 3D Ligand-Based Virtual Screening Method

Herein, we report the discovery of the first potent and selective inhibitor of TRPV6, a calcium channel overexpressed in breast and prostate cancer, and its use to test the effect of blocking TRPV6-mediated Ca2+-influx on cell growth. The inhibitor was discovered through a computational method, xLOS, a 3D-shape and pharmacophore similarity algorithm, a type of ligand-based virtual screening (LBVS) method described briefly here. Starting with a single weakly active seed molecule, two successive rounds of LBVS followed by optimization by chemical synthesis led to a selective molecule with 0.3 μM inhibition of TRPV6. The ability of xLOS to identify different scaffolds early in LBVS was essential to success. The xLOS method may be generally useful to develop tool compounds for poorly characterized targets.

Selective mortality associated with variation in CO2 tolerance in a marine fish

Predicted future CO2 levels can affect reproduction, growth, and behaviour of many marine organisms. However, the capacity of species to adapt to predicted changes in ocean chemistry is largely unknown. We used a unique field-based experiment to test for differential survival associated with variation in CO2 tolerance in a wild population of coral-reef fishes. Juvenile damselfish exhibited variation in their response to elevated (700 µatm) CO2 when tested in the laboratory and this influenced their behaviour and risk of mortality in the wild. Individuals that were sensitive to elevated CO2 were more active and move further from shelter in natural coral reef habitat and, as a result, mortality from predation was significantly higher compared with individuals from the same treatment that were tolerant of elevated CO2. If individual variation in CO2 tolerance is heritable, this selection of phenotypes tolerant to elevated CO2 could potentially help mitigate the effects of ocean acidification.

Anticorrelation between Ion Acceleration and Nonlinear Coherent Structures from Laser-Underdense Plasma Interaction

In laser-plasma experiments, we observed that ion acceleration from the Coulomb explosion of the plasma channel bored by the laser, is prevented when multiple plasma instabilities such as filamentation and hosing, and nonlinear coherent structures (vortices/post-solitons) appear in the wake of an ultrashort laser pulse. The tailoring of the longitudinal plasma density ramp allows us to control the onset of these insabilities. We deduced that the laser pulse is depleted into these structures in our conditions, when a plasma at about 10% of the critical density exhibits a gradient on the order of 250 {\mu}m (gaussian fit), thus hindering the acceleration. A promising experimental setup with a long pulse is demonstrated enabling the excitation of an isolated coherent structure for polarimetric measurements and, in further perspectives, parametric studies of ion plasma acceleration efficiency.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Distinguishing surface effects of calcium ion from pore-occupancy effects in Na+ channels

The effects of calcium ion on the Na+ activation gate were studied in squid giant axons. Saxitoxin (STX) was used to block ion entry into Na+ channels without hindering access to the membrane surface, making it possible to distinguish surface effects of calcium from pore-occupancy effects. In the presence of STX, gating kinetics were measured from gating current (Ig). The kinetic effects of external calcium concentration changes were small when STX was present. In the absence of STX, lowering the calcium concentration (from 100 to 10 mM) slowed the closing of Na+ channels (measured from INa tails) by more than a factor of 2. Surprisingly, the voltage sensitivity of closing kinetics changed with calcium concentration, and it was modified by STX. Voltage sensitivity apparently depends in part on the ability of calcium to enter and block the channels as voltage is driven negative. In external medium with no added calcium, INa tail current initially increases in amplitude severalfold with the relief of calcium block, then progressively slows and gets smaller, as calcium diffuses out of the layers investing the axon. INa tails seen just before the current disappears suggest that closing in the absence of channel block is very slow or does not occur. INa amplitude and kinetics are completely restored when calcium is returned. The results strongly suggest that calcium occupancy is a requirement for channel closing and that nonoccupied channels fold reversibly into a nonfunctional conformation.

Isolation of a myoglobin molten globule by selective cobalt(III)-induced unfolding

Reaction of the Schiff-base complex [Co(acetylacetonate-ethylenediimine)(NH3)2]+ with metmyoglobin at pH 6.5 yields a partially folded protein containing six Co(III) complexes. Although half of its α-helical secondary structure is retained, absorption and CD spectra indicate that the tertiary structure in both B-F and AGH domains is disrupted in the partially folded protein. In analogy to proton-induced unfolding, it is likely that the loss of tertiary structure is triggered by metal-ion binding to histidines. Cobalt(III)-induced unfolding of myoglobin is unique in its selectivity (other proteins are unaffected) and in allowing the isolation of the partially folded macromolecule (the protein does not refold or aggregate upon removal of free denaturant).

Induction of epithelial chloride secretion by channel-forming cryptdins 2 and 3

Salt and water secretion from intestinal epithelia requires enhancement of anion permeability across the apical membrane of Cl− secreting cells lining the crypt, the secretory gland of the intestine. Paneth cells located at the base of the small intestinal crypt release enteric defensins (cryptdins) apically into the lumen. Because cryptdins are homologs of molecules known to form anion conductive pores in phospholipid bilayers, we tested whether these endogenous antimicrobial peptides could act as soluble inducers of channel-like activity when applied to apical membranes of intestinal Cl− secreting epithelial cells in culture. Of the six peptides tested, cryptdins 2 and 3 stimulated Cl− secretion from polarized monolayers of human intestinal T84 cells. The response was reversible and dose dependent. In contrast, cryptdins 1, 4, 5, and 6 lacked this activity, demonstrating that Paneth cell defensins with very similar primary structures may exhibit a high degree of specificity in their capacity to elicit Cl− secretion. The secretory response was not inhibited by pretreatment with 8-phenyltheophyline (1 μM), or dependent on a concomitant rise in intracellular cAMP or cGMP, indicating that the apically located adenosine and guanylin receptors were not involved. On the other hand, cryptdin 3 elicited a secretory response that correlated with the establishment of an apically located anion conductive channel permeable to carboxyfluorescein. Thus cryptdins 2 and 3 can selectively permeabilize the apical cell membrane of epithelial cells in culture to elicit a physiologic Cl− secretory response. These data define the capability of cryptdins 2 and 3 to function as novel intestinal secretagogues, and suggest a previously undescribed mechanism of paracrine signaling that in vivo may involve the reversible formation of ion conductive channels by peptides released into the crypt microenvironment.