PV self-consumption optimization with storage and Active DSM for the residential sector

With the rising prices of the retail electricity and the decreasing cost of the PV technology, grid parity with commercial electricity will soon become a reality in Europe. This fact, together with less attractive PV feed-in-tariffs in the near future and incentives to promote self-consumption suggest, that new operation modes for the PV Distributed Generation should be explored; differently from the traditional approach which is only based on maximizing the exported electricity to the grid. The smart metering is experiencing a growth in Europe and the United States but the possibilities of its use are still uncertain, in our system we propose their use to manage the storage and to allow the user to know their electrical power and energy balances. The ADSM has many benefits studied previously but also it has important challenges, in this paper we can observe and ADSM implementation example where we propose a solution to these challenges. In this paper we study the effects of the Active Demand-Side Management (ADSM) and storage systems in the amount of consumed local electrical energy. It has been developed on a prototype of a self-sufficient solar house called “MagicBox” equipped with grid connection, PV generation, lead–acid batteries, controllable appliances and smart metering. We carried out simulations for long-time experiments (yearly studies) and real measures for short and mid-time experiments (daily and weekly studies). Results show the relationship between the electricity flows and the storage capacity, which is not linear and becomes an important design criterion.

Non-destructive measurements of the optical properties of apples by means of time-resolved reflectance

Time-resolved reflectance is proposed and effectively used for the nondestructive measurement of the optical properties in apples. The technique is based on the detection of the temporal dispersion of a short laser pulse injected into the probed medium. The time-distribution of re-emitted photons interpreted with a solution of the Diffusion equation yields the mean values of the absorption and reduced scattering coefficients of the medium. The proposed technique proved valuable for the measurement of the absorption and scattering spectra of different varieties of apples. No major variations were observed in the experimental data when the fruit was peeled, proving that the measured optical properties are referred to the pulp. The depth of probed volume was determined to be about 2 cm. Finally, the technique proved capable to follow the change in chlorophyll absorption during storage.

Non-destructive measurements of the optical properties of apples by means of time-resolved reflectance

Time-resolved reflectance is proposed and effectively used for the nondestructive measurement of the optical properties in apples. The technique is based on the detection of the temporal dispersion of a short laser pulse injected into the probed medium. The time-distribution of re-emitted photons interpreted with a solution of the Diffusion equation yields the mean values of the absorption and reduced scattering coefficients of the medium. The proposed technique proved valuable for the measurement of the absorption and scattering spectra of different varieties of apples. No major variations were observed in the experimental data when the fruit was peeled, proving that the measured optical properties are referred to the pulp. The depth of probed volume was determined to be about 2 cm. Finally, the technique proved capable to follow the change in chlorophyll absorption during storage.

Harmony: Towards automated self-adaptive consistency in cloud storage

In just a few years cloud computing has become a very popular paradigm and a business success story, with storage being one of the key features. To achieve high data availability, cloud storage services rely on replication. In this context, one major challenge is data consistency. In contrast to traditional approaches that are mostly based on strong consistency, many cloud storage services opt for weaker consistency models in order to achieve better availability and performance. This comes at the cost of a high probability of stale data being read, as the replicas involved in the reads may not always have the most recent write. In this paper, we propose a novel approach, named Harmony, which adaptively tunes the consistency level at run-time according to the application requirements. The key idea behind Harmony is an intelligent estimation model of stale reads, allowing to elastically scale up or down the number of replicas involved in read operations to maintain a low (possibly zero) tolerable fraction of stale reads. As a result, Harmony can meet the desired consistency of the applications while achieving good performance. We have implemented Harmony and performed extensive evaluations with the Cassandra cloud storage on Grid?5000 testbed and on Amazon EC2. The results show that Harmony can achieve good performance without exceeding the tolerated number of stale reads. For instance, in contrast to the static eventual consistency used in Cassandra, Harmony reduces the stale data being read by almost 80% while adding only minimal latency. Meanwhile, it improves the throughput of the system by 45% while maintaining the desired consistency requirements of the applications when compared to the strong consistency model in Cassandra.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Storage stability of SBS/sulfur modified bitumens at high temperature: influence of bitumen composition and structure

Polymer modified bitumens, PMBs, are usually prepared at high temperature and subsequently stored for a period of time, also at high temperature. The stability of PMBs, in these conditions, has a decisive influence in order to obtain the adequate performances for practical applications. In this article the attention is focused in the analysis of the factors that determine the stability of styrene–butadiene–styrene copolymer (SBS)/sulfur modified bitumens when the mixtures are maintained at high temperature. Bitumens from different crude oil sources were used to prepare SBS/sulfur modified bitumens. Changes in the values of viscosity, softening point, as well as in the morphology of PMB samples, stored at 160 °C, were related to the bitumen chemical composition and to the amount of asphaltene micelles present in the neat bitumen used in their preparation El trabajo se centra en el estudio de la influencia de la estructura /composición del betún sobre la compatibilidad del sistema betún/SBS. Cuatro betunes provenientes de dos crudos distintos se seleccionaron y sus mezclas se utilizaron para preparar betunes modificados con contenidos de SBS del 3% en peso

Steady state analysis of a storage integrated solar thermophotovoltaic (SISTPV) system

This paper presents the theoretical analysis of a storage integrated solar thermophotovoltaic (SISTPV) system operating in steady state. These systems combine thermophotovoltaic (TPV) technology and high temperature thermal storage phase-change materials (PCM) in the same unit, providing a great potential in terms of efficiency, cost reduction and storage energy density. The main attraction in the proposed system is its simplicity and modularity compared to conventional Concentrated Solar Power (CSP) technologies. This is mainly due to the absence of moving parts. In this paper we analyze the use of Silicon as the phase change material (PCM). Silicon is an excellent candidate because of its high melting point (1680 K) and its very high latent heat of fusion of 1800 kJ/kg, which is about ten times greater than the conventional PCMs like molten salts. For a simple system configuration, we have demonstrated that overall conversion efficiencies up to ?35% are approachable. Although higher efficiencies are expected by incorporating more advanced devices like multijunction TPV cells, narrow band selective emitters or adopting near-field TPV configurations as well as by enhancing the convective/conductive heat transfer within the PCM. In this paper, we also discuss about the optimum system configurations and provide the general guidelines for designing these systems. Preliminary estimates of night time operations indicate it is possible to achieve over 10 h of operation with a relatively small quantity of Silicon.

Influence of duration of storage on protein quality traits of soybean meals

Two experiments were conducted to determine the influence of duration of storage of soybean meal (SBM) on variables that define the quality of the protein fraction. Urease activity, protein dispersibility index (PDI), KOH protein solubility (KOHsol), and trypsin inhibitor activity were determined. In experiment 1, 8 samples of SBM, ranging in CP content from 55.4 to 56.5% DM, were collected from a US crushing plant at weekly intervals and analyzed at arrival to the laboratory and after 30, 60, 90, and 120 d of storage. In experiment 2, 7 samples of SBM, ranging in CP content from 49.0 to 55.0% DM, were collected from different Argentinean crushers and analyzed at arrival and after 24, 48, 80, and 136 wk of storage. In both experiments, samples were stored in hermetic glass containers in a laboratory room at 12 ± 2°C and a relative humidity of 70 ± 3%. Duration of storage did not affect urease activity or trypsin inhibitor activity values in either of the 2 experiments. However, PDI values decreased linearly with time of storage in both experiments (P menor que 0.001). Also, KOHsol decreased linearly (P menor que 0.05) with duration of storage in experiment 2 (long-term storage) but not in experiment 1(shorter term storage). Therefore, PDI values might not be adequate to compare protein quality of commercial SBM samples that have been stored for different periods of time. The KOHsol values are less affected by length of storage of the meals under current commercial practices.

Improving photovoltaics grid integration through short time forecasting and self-consumption

The uncertainty associated to the forecast of photovoltaic generation is a major drawback for the widespread introduction of this technology into electricity grids. This uncertainty is a challenge in the design and operation of electrical systems that include photovoltaic generation. Demand-Side Management (DSM) techniques are widely used to modify energy consumption. If local photovoltaic generation is available, DSM techniques can use generation forecast to schedule the local consumption. On the other hand, local storage systems can be used to separate electricity availability from instantaneous generation; therefore, the effects of forecast error in the electrical system are reduced. The effects of uncertainty associated to the forecast of photovoltaic generation in a residential electrical system equipped with DSM techniques and a local storage system are analyzed in this paper. The study has been performed in a solar house that is able to displace a residential user?s load pattern, manage local storage and estimate forecasts of electricity generation. A series of real experiments and simulations have carried out on the house. The results of this experiments show that the use of Demand Side Management (DSM) and local storage reduces to 2% the uncertainty on the energy exchanged with the grid. In the case that the photovoltaic system would operate as a pure electricity generator feeding all generated electricity into grid, the uncertainty would raise to around 40%.

Real time monitoring of click chemistry self-healing in polymer composites

A photo-healable rubber composite based on effective and fast thiol-alkyne click chemistry as a selfhealing agent prestored in glass capillaries is reported. The click reaction and its effect on the mechanical properties of the composite are monitored in real time by dynamic mechanical analysis, showing that the successful bleeding of healing agents to the crack areas and the effective photoinitiated click reaction result in a 30% storage modulus increase after only 5 min of UV light exposure. X-ray tomography confirms capillary-driven bleeding of reactants to the damaged areas. The effect of storing the click chemistry reactants in separate capillaries is also studied, and results show the importance of stoichiometry in achieving a significant level of repair of the composite. No reactant degradation or premature chemical reaction is observed over time in samples stored in the absence of UV radiation; they are able to undergo the self-healing reaction even one month after preparation.

Synthesis, Storage, and Release of Vascular Endothelial Growth Factor/Vascular Permeability Factor (VEGF/VPF) by Human Mast Cells: Implications for the Biological Significance of VEGF206

Mast cells have been implicated in various diseases that are accompanied by neovascularization. The exact mechanisms by which mast cells might mediate an angiogenic response, however, are unclear and therefore, we have investigated the possible expression of vascular endothelial growth factor/vascular permeability factor (VEGF/VPF) in the human mast cell line HMC-1 and in human skin mast cells. Reverse transcription-polymerase chain reaction (RT-PCR) analysis revealed that mast cells constitutively express VEGF121, VEGF165, and VEGF189. After a prolonged stimulation of cells for 24 h with phorbol 12-myristate 13-acetate (PMA) and the ionophore A23187, an additional transcript representing VEGF206 was detectable, as could be verified by sequence analysis. These results were confirmed at the protein level by Western blot analysis. When the amounts of VEGF released under unstimulated and stimulated conditions were compared, a significant increase was detectable after stimulation of cells. Human microvascular endothelial cells (HMVEC) responded to the supernatant of unstimulated HMC-1 cells with a dose-dependent mitogenic effect, neutralizable up to 90% in the presence of a VEGF-specific monoclonal antibody. Flow cytometry and postembedding immunoelectron microscopy were used to detect VEGF in its cell-associated form. VEGF was exclusively detectable in the secretory granules of isolated human skin mast cells. These results show that both normal and leukemic human mast cells constitutively express bioactive VEGF. Furthermore, this study contributes to the understanding of the physiological role of the strongly heparin-binding VEGF isoforms, since these were found for the first time to be expressed in an activation-dependent manner in HMC-1 cells.

Characterization of SU1 Isoamylase, a Determinant of Storage Starch Structure in Maize1

Function of the maize (Zea mays) gene sugary1 (su1) is required for normal starch biosynthesis in endosperm. Homozygous su1- mutant endosperms accumulate a highly branched polysaccharide, phytoglycogen, at the expense of the normal branched component of starch, amylopectin. These data suggest that both branched polysaccharides share a common precursor, and that the product of the su1 gene, designated SU1, participates in kernel starch biosynthesis. SU1 is similar in sequence to α-(1→6) glucan hydrolases (starch-debranching enzymes [DBEs]). Specific antibodies were produced and used to demonstrate that SU1 is a 79-kD protein that accumulates in endosperm coincident with the time of starch biosynthesis. Nearly full-length SU1 was expressed in Escherichia coli and purified to apparent homogeneity. Two biochemical assays confirmed that SU1 hydrolyzes α-(1→6) linkages in branched polysaccharides. Determination of the specific activity of SU1 toward various substrates enabled its classification as an isoamylase. Previous studies had shown, however, that su1- mutant endosperms are deficient in a different type of DBE, a pullulanase (or R enzyme). Immunoblot analyses revealed that both SU1 and a protein detected by antibodies specific for the rice (Oryza sativa) R enzyme are missing from su1- mutant kernels. These data support the hypothesis that DBEs are directly involved in starch biosynthesis.

Bathorhodopsin structure in the room-temperature rhodopsin photosequence: picosecond time-resolved coherent anti-Stokes Raman scattering.

Structural changes in the retinal chromophore during the formation of the bathorhodopsin intermediate (bathoRT) in the room-temperature rhodopsin (RhRT) photosequence (i.e., vision) are examined using picosecond time-resolved coherent anti-Stokes Raman scattering. Specifically, the retinal structure assignable to bathoRT following 8-ps excitation of RhRT is measured via vibrational Raman spectroscopy at a 200-ps time delay where the only intermediate present is bathoRT. Significant differences are observed between the C=C stretching frequencies of the retinal chromophore at low temperature where bathorhodopsin is stabilized and at room temperature where bathorhodopsin is a transient species in the RhRT photosequence. These vibrational data are discussed in terms of the formation of bathoRT, an important step in the energy storage/transduction mechanism of RhRT.

Lipoxygenase-catalyzed oxygenation of storage lipids is implicated in lipid mobilization during germination.

The etiolated germination process of oilseed plants is characterized by the mobilization of storage lipids, which serve as a major carbon source for the seedling. We found that during early stages of germination in cucumber, a lipoxygenase (linoleate: oxygen oxidoreductase, EC 1.13.11.12) form is induced that is capable of oxygenating the esterified fatty acids located in the lipid-storage organelles, the so-called lipid bodies. Large amounts of esterified (13S)-hydroxy-(9Z,11E)-octadecadienoic acid were detected in the lipid bodies, whereas only traces of other oxygenated fatty acid isomers were found. This specific product pattern confirms the in vivo action of this lipoxygenase form during germination. Lipid fractionation studies of lipid bodies indicated the presence of lipoxygenase products both in the storage triacylglycerols and, to a higher extent, in the phospholipids surrounding the lipid stores as a monolayer. The degree of oxygenation of the storage lipids increased drastically during the time course of germination. We show that oxygenated fatty acids are preferentially cleaved from the lipid bodies and are subsequently released into the cytoplasm. We suggest that they may serve as substrate for beta-oxidation. These data suggest that during the etiolated germination, a lipoxygenase initiates the mobilization of storage lipids. The possible mechanisms of this implication are discussed.

High-Pressure Methane Storage in Porous Materials: Are Carbon Materials in the Pole Position?

Natural gas storage on porous materials (ANG) is a promising alternative to conventional on-board compressed (CNG) or liquefied natural gas (LNG). To date, Metal–organic framework (MOF) materials have apparently been the only system published in the literature that is able to reach the new Department of Energy (DOE) value of 263 cm3 (STP: 273.15 K, 1 atm)/cm3; however, this value was obtained by using the ideal single-crystal density to calculate the volumetric capacity. Here, we prove experimentally, and for the first time, that properly designed activated carbon materials can really achieve the new DOE value while avoiding the additional drawback usually associated with MOF materials (i.e., the low mechanical stability under pressure (conforming), which is required for any practical application).