Adaptivity in programming languages

A programming style can be seen as a particular model of shaping thought or a special way of codifying language to solve a problem. An adaptive device is made up of an underlying formalism, for instance, an automaton, a grammar, a decision tree, etc., and an adaptive mechanism, responsible for providing features for self-modification. Adaptive languages are obtained by using some programming language as the device’s underlying formalism. The conception of such languages calls for a new programming style, since the application of adaptive technology in the field of programming languages suggests a new way of thinking. Adaptive languages have the basic feature of allowing the expression of programs which self-modifying through adaptive actions at runtime. With the adaptive style, programming language codes can be structured in such a way that the codified program therein modifies or adapts itself towards the needs of the problem. The adaptive programming style may be a feasible alternate way to obtain self-modifying consistent codes, which allow its use in modern applications for self-modifying code.

Adaptive device with underlying mechanism defined by a programming language

An adaptive device is made up of an underlying mechanism, for instance, an automaton, a grammar, a decision tree, etc., to which is added an adaptive mechanism, responsible for allowing a dynamic modification in the structure of the underlying mechanism. This article aims to investigate if a programming language can be used as an underlying mechanism of an adaptive device, resulting in an adaptive language.

Conception of adaptive programming languages

Adaptive devices show the characteristic of dynamically change themselves in response to input stimuli with no interference of external agents. Occasional changes in behaviour are immediately detected by the devices, which right away react spontaneously to them. Chronologically such devices derived from researches in the field of formal languages and automata. However, formalism spurred applications in several other fields. Based on the operation of adaptive automata, the elementary ideas generanting programming adaptive languages are presented.

Adaptive languages and a new programming style

A programming style can be seen as a particular model of shaping thought or a special way of codifying language to solve a problem. Adaptive languages have the basic feature of allowing the expression of programs which self-modifying through adaptive actions at runtime. The conception of such languages calls for a new programming style, since the application of adaptive technology in the field of programming languages suggests a new way of thinking. With the adaptive style, programming language codes can be structured in such a way that the codified program therein modifies or adapts itself towards the needs of the problem. The adaptive programming style may be a feasible alternate way to obtain self-modifying consistent codes, which allow its use in modern applications for self-modifying code.

Using adaptive automata in a multi-paradigm programming environment

In this paper the architecture of an experimental multiparadigmatic programming environment is sketched, showing how its parts combine together with application modules in order to perform the integration of program modules written in different programming languages and paradigms. Adaptive automata are special self-modifying formal state machines used as a design and implementation tool in the representation of complex systems. Adaptive automata have been proven to have the same formal power as Turing Machines. Therefore, at least in theory, arbitrarily complex systems may be modeled with adaptive automata. The present work briefly introduces such formal tool and presents case studies showing how to use them in two very different situations: the first one, in the name management module of a multi-paradigmatic and multi-language programming environment, and the second one, in an application program implementing an adaptive automaton that accepts a context-sensitive language.

Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip

The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

Teste da rede de interconexões de field programmable analog arrays

Os dispositivos analógicos programáveis (FPAAs, do inglês, Field Programmable Analog Arrays), apesar de ainda não terem a mesma popularidade de seus pares digitais (FPGAs, do inglês, Field Programmable Gate Arrays), possuem uma gama de aplicações bastante ampla, que vai desde o condicionamento de sinais em sistemas de instrumentação, até o processamento de sinais de radiofreqüência (RF) em telecomunicações. Porém, ao mesmo tempo em que os FPAAs trouxeram um impressionante ganho na agilidade de concepção de circuitos analógicos, também trouxeram um conjunto de novos problemas relativos ao teste deste tipo de dispositivo. Os FPAAs podem ser divididos em duas partes fundamentais: seus blocos programáveis básicos (CABs, do inglês, Configurable Analog Blocks) e sua rede de interconexões. A rede de interconexões, por sua vez, pode ser dividida em duas partes: interconexões internas (locais e globais entre CABs) e interconexões externas (envolvendo células de I/O). Todas estas partes apresentam características estruturais e funcionais distintas, de forma que devem ser testadas separadamente, pois necessitam que se considerem modelos de falhas, configurações e estímulos de teste específicos para assegurar uma boa taxa de detecção de defeitos. Como trabalhos anteriores já estudaram o teste dos CABs, o foco desta dissertação está direcionado ao desenvolvimento de metodologias que se propõem a testar a rede de interconexões de FPAAs. Apesar das várias diferenças entre as redes de interconexões de FPGAs e FPAAs, muitas também são as semelhanças entre elas, sendo, portanto, indiscutível que o ponto de partida deste trabalho tenha que ser o estudo das muitas técnicas propostas para o teste de interconexões em FPGAs, para posterior adaptação ao caso dos FPAAs. Além disto, embora o seu foco não recaia sobre o teste de CABs, pretende-se utilizá-los como recursos internos do dispositivo passíveis de gerar sinais e analisar respostas de teste, propondo uma abordagem de auto-teste integrado de interconexões que reduza o custo relativo ao equipamento externo de teste. Eventualmente, estes mesmos recursos poderão também ser utilizados para diagnóstico das partes defeituosas. Neste trabalho, utiliza-se como veículo de experimentação um dispositivo específico (Anadigm AN10E40), mas pretende-se que as metodologias de teste propostas sejam abrangentes e possam ser facilmente adaptadas a outros FPAAs comerciais que apresentem redes de interconexão semelhantes.