Fiber Bragg grating structures inscribed using 800nm femtosecond laser in single- and multi-core mid-IR glass fibers with their spectral, thermal and strain properties

Single- and multi-core passive and active germanate and tellurite glass fibers represent a new class of fiber host for in-fiber photonics devices and applications in mid-IR wavelength range, which are in increasing demand. Fiber Bragg grating (FBG) structures have been proven as one of the most functional in-fiber devices and have been mass-produced in silicate fibers by UV-inscription for almost countless laser and sensor applications. However, because of the strong UV absorption in germanate and tellurite fibers, FBG structures cannot be produced by UVinscription. In recent years femtosecond (fs) lasers have been developed for laser machining and microstructuring in a variety of glass fibers and planar substrates. A number of papers have been reported on fabrication of FBGs and long-period gratings in optical fibers and also on the photosensitivity mechanism using 800nm fs lasers. In this paper, we demonstrate for the first time the fabrication of FBG structures created in passive and active single- and three-core germanate and tellurite glass fibers by using 800nm fs-inscription and phase mask technique. With a fs peak power intensity in the order of 1011W/cm2, the FBG spectra with 2nd and 3rd order resonances at 1540nm and 1033nm in a single-core germanate glass fiber and 2nd order resonances between ~1694nm and ~1677nm with strengths up to 14dB in all three cores of three-core passive and active tellurite fibers were observed. Thermal and strain properties of the FBGs made in these mid-IR glass fibers were characterized, showing an average temperature responsivity of ~20pm/°C and a strain sensitivity of 1.219±0.003pm/µe.

Fiber Bragg gratings inscribed using 800nm femtosecond laser and a phase mask in singleand multi-core mid-IR glass fibers

For the first time, Fiber Bragg grating (FBG) structures have been inscribed in single-core passive germanate and three-core passive and active tellurite glass fibers using 800 nm femtosecond (fs) laser and phase mask technique. With fs peak power intensity in the order of 10(11)W/cm(2), the FBG spectra with 2nd and 3rd order resonances at 1540 and 1033 nm in the germanate glass fiber and 2nd order resonances at approximately 1694 and approximately 1677 nm with strengths up to 14 dB in all three cores in the tellurite fiber were observed. Thermal responsivities of the FBGs made in these mid-IR glass fibers were characterized, showing average temperature responsivity approximately 20 pm/ degrees C. Strain responsivities of the FBGs in germanate glass fiber were measured to be 1.219 pm/microepsilon.

Nonlinear pulse combining and pulse compression in multi-core fibers

We demonstrate light pulse combining and pulse compression using a continuous-discrete nonlinear system implemented in a multi-core fiber (MCF). It is shown that the pulses initially injected into all of the cores of a ring MCF are combined by nonlinearity into a small number of cores with simultaneous pulse compression. We demonstrate the combining of 77% of the energy into one core with pulse compression over 14× in a 20-core MCF. We also demonstrate that a suggested scheme is insensitive to the phase perturbations. Nonlinear spatio-temporal pulse manipulation in multi-core fibers can be exploited for various applications, including pulse compression, switching, and combining.

Temperature management for heterogeneous multi-core FPGAs using adaptive evolutionary multi-objective approaches

Heterogeneous multi-core FPGAs contain different types of cores, which can improve efficiency when used with an effective online task scheduler. However, it is not easy to find the right cores for tasks when there are multiple objectives or dozens of cores. Inappropriate scheduling may cause hot spots which decrease the reliability of the chip. Given that, our research builds a simulating platform to evaluate all kinds of scheduling algorithms on a variety of architectures. On this platform, we provide an online scheduler which uses multi-objective evolutionary algorithm (EA). Comparing the EA and current algorithms such as Predictive Dynamic Thermal Management (PDTM) and Adaptive Temperature Threshold Dynamic Thermal Management (ATDTM), we find some drawbacks in previous work. First, current algorithms are overly dependent on manually set constant parameters. Second, those algorithms neglect optimization for heterogeneous architectures. Third, they use single-objective methods, or use linear weighting method to convert a multi-objective optimization into a single-objective optimization. Unlike other algorithms, the EA is adaptive and does not require resetting parameters when workloads switch from one to another. EAs also improve performance when used on heterogeneous architecture. A efficient Pareto front can be obtained with EAs for the purpose of multiple objectives.

An integrated multi-agent framework for optimizing time, cost and environmental impact of construction processes

Environmentally conscious construction has received a significant amount of research attention during the last decades. Even though construction literature is rich in studies that emphasize the importance of environmental impact during the construction phase, most of the previous studies failed to combine environmental analysis with other project performance criteria in construction. This is mainly because most of the studies have overlooked the multi-objective nature of construction projects. In order to achieve environmentally conscious construction, multi-objectives and their relationships need to be successfully analyzed in the complex construction environment. The complex construction system is composed of changing project conditions that have an impact on the relationship between time, cost and environmental impact (TCEI) of construction operations. Yet, this impact is still unknown by construction professionals. Studying this impact is vital to fulfill multiple project objectives and achieve environmentally conscious construction. This research proposes an analytical framework to analyze the impact of changing project conditions on the relationship of TCEI. This study includes green house gas (GHG) emissions as an environmental impact category. The methodology utilizes multi-agent systems, multi-objective optimization, analytical network process, and system dynamics tools to study the relationships of TCEI and support decision-making under the influence of project conditions. Life cycle assessment (LCA) is applied to the evaluation of environmental impact in terms of GHG. The mixed method approach allowed for the collection and analysis of qualitative and quantitative data. Structured interviews of professionals in the highway construction field were conducted to gain their perspectives in decision-making under the influence of certain project conditions, while the quantitative data were collected from the Florida Department of Transportation (FDOT) for highway resurfacing projects. The data collected were used to test the framework. The framework yielded statistically significant results in simulating project conditions and optimizing TCEI. The results showed that the change in project conditions had a significant impact on the TCEI optimal solutions. The correlation between TCEI suggested that they affected each other positively, but in different strengths. The findings of the study will assist contractors to visualize the impact of their decision on the relationship of TCEI.

Real-time scheduling of embedded applications on multi-core platforms

For the past several decades, we have experienced the tremendous growth, in both scale and scope, of real-time embedded systems, thanks largely to the advances in IC technology. However, the traditional approach to get performance boost by increasing CPU frequency has been a way of past. Researchers from both industry and academia are turning their focus to multi-core architectures for continuous improvement of computing performance. In our research, we seek to develop efficient scheduling algorithms and analysis methods in the design of real-time embedded systems on multi-core platforms. Real-time systems are the ones with the response time as critical as the logical correctness of computational results. In addition, a variety of stringent constraints such as power/energy consumption, peak temperature and reliability are also imposed to these systems. Therefore, real-time scheduling plays a critical role in design of such computing systems at the system level. We started our research by addressing timing constraints for real-time applications on multi-core platforms, and developed both partitioned and semi-partitioned scheduling algorithms to schedule fixed priority, periodic, and hard real-time tasks on multi-core platforms. Then we extended our research by taking temperature constraints into consideration. We developed a closed-form solution to capture temperature dynamics for a given periodic voltage schedule on multi-core platforms, and also developed three methods to check the feasibility of a periodic real-time schedule under peak temperature constraint. We further extended our research by incorporating the power/energy constraint with thermal awareness into our research problem. We investigated the energy estimation problem on multi-core platforms, and developed a computation efficient method to calculate the energy consumption for a given voltage schedule on a multi-core platform. In this dissertation, we present our research in details and demonstrate the effectiveness and efficiency of our approaches with extensive experimental results.

Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.

Visual programming in a heterogeneous multi-core environment

É do conhecimento geral de que, hoje em dia, a tecnologia evolui rapidamente. São criadas novas arquitecturas para resolver determinadas limitações ou problemas. Por vezes, essa evolução é pacífica e não requer necessidade de adaptação e, por outras, essa evolução pode Implicar mudanças. As linguagens de programação são, desde sempre, o principal elo de comunicação entre o programador e o computador. Novas linguagens continuam a aparecer e outras estão sempre em desenvolvimento para se adaptarem a novos conceitos e paradigmas. Isto requer um esforço extra para o programador, que tem de estar sempre atento a estas mudanças. A Programação Visual pode ser uma solução para este problema. Exprimir funções como módulos que recebem determinado Input e retomam determinado output poderá ajudar os programadores espalhados pelo mundo, através da possibilidade de lhes dar uma margem para se abstraírem de pormenores de baixo nível relacionados com uma arquitectura específica. Esta tese não só mostra como combinar as capacidades do CeII/B.E. (que tem uma arquitectura multi­processador heterogénea) com o OpenDX (que tem um ambiente de programação visual), como também demonstra que tal pode ser feito sem grande perda de performance. ABSTRACT; lt is known that nowadays technology develops really fast. New architectures are created ln order to provide new solutions for different technology limitations and problems. Sometimes, this evolution is pacific and there is no need to adapt to new technologies, but things also may require a change every once ln a while. Programming languages have always been the communication bridge between the programmer and the computer. New ones keep coming and other ones keep improving ln order to adapt to new concepts and paradigms. This requires an extra-effort for the programmer, who always needs to be aware of these changes. Visual Programming may be a solution to this problem. Expressing functions as module boxes which receive determined Input and return determined output may help programmers across the world by giving them the possibility to abstract from specific low-level hardware issues. This thesis not only shows how the CeII/B.E. (which has a heterogeneous multi-core architecture) capabilities can be combined with OpenDX (which has a visual programming environment), but also demonstrates that lt can be done without losing much performance.

Progetto di Sistemi di Regolazione dell'Alimentazione ad Alta Affidabilità per Processori Multi-Core

Quasi tutti i componenti del FIVR (regolatore di tensione Buck che fornisce l'alimentazione ai microprocessori multi-core) sono implementati sul die del SoC e quindi soffrono di problemi di affidabilità associati allo scaling della tecnologia microelettronica. In particolare, la variazione dei parametri di processo durante la fabbricazione e i guasti nei dispostivi di switching (circuiti aperti o cortocircuiti). Questa tesi si svolge in ambito di un progetto di ricerca in collaborazione con Intel Corporation, ed è stato sviluppato in due parti: Inizialmente è stato arricchito il lavoro di analisi dei guasti su FIVR, svolgendo un accurato studio su quelli che sono i principali effetti dell’invecchiamento sulle uscite dei regolatori di tensione integrati su chip. Successivamente è stato sviluppato uno schema di monitoraggio a basso costo in grado di rilevare gli effetti dei guasti più probabili del FIVR sul campo. Inoltre, lo schema sviluppato è in grado di rilevare, durante il tempo di vita del FIVR, gli effetti di invecchiamento che inducono un incorretto funzionamento del FIVR. Lo schema di monitoraggio è stato progettato in maniera tale che risulti self-checking nei confronti dei suoi guasti interni, questo per evitare che tali errori possano compromettere la corretta segnalazione di guasti sul FIVR.

Sistemi di Regolazione dell'Alimentazione Affidabili per Processori Multi-Core

I moderni processori multi-core ad elevate prestazioni sono alimentati da regolatori di tensione integrati direttamente sul chip. Questi regolatori forniscono a ciascun power domain la tensione ottimale sulla base della sua attività, monitorata da una Power Control Unit. Questo consente da un lato di ottenere una riduzione dei consumi, dall'altro di avere un boost delle prestazioni in particolari contesti. Tali regolatori integrati sul die sono affetti da guasti e fenomeni di aging, che possono compromettere il corretto funzionamento del circuito. Questi problemi non sono tollerabili in contesti caratterizzati da esigenze di elevata reliability, come l'autonomous driving. Dunque, è stato sviluppato un monitor per rivelare on-line eventuali guasti che possono verificarsi durante il normale funzionamento sul campo. In caso di guasto il monitor è in grado di dare un'indicazione d'errore, che può essere utilizzata per attivare delle procedure di recovery. La soluzione proposta, basata su un approccio completamente differente rispetto a quello suggerito dallo standard ISO 26262, beneficia, rispetto a quest'ultima, di costi nettamente inferiori e prestazioni superiori. Il monitor può essere calibrato automaticamente per compensare le variazioni dei parametri di processo ed i fenomeni di aging che possono affliggere il monitor stesso. È stata verificata la self-checking ability del monitor rispetto a guasti di tipo transistor stuck-on, transistor stuck-open e bridging resistivo, risultando Totally Self-Checking rispetto all'insieme di guasti considerato.

High performance and energy-efficient instruction cache design and optimisation for ultra-low-power multi-core clusters

High Energy efficiency and high performance are the key regiments for Internet of Things (IoT) end-nodes. Exploiting cluster of multiple programmable processors has recently emerged as a suitable solution to address this challenge. However, one of the main bottlenecks for multi-core architectures is the instruction cache. While private caches fall into data replication and wasting area, fully shared caches lack scalability and form a bottleneck for the operating frequency. Hence we propose a hybrid solution where a larger shared cache (L1.5) is shared by multiple cores connected through a low-latency interconnect to small private caches (L1). However, it is still limited by large capacity miss with a small L1. Thus, we propose a sequential prefetch from L1 to L1.5 to improve the performance with little area overhead. Moreover, to cut the critical path for better timing, we optimized the core instruction fetch stage with non-blocking transfer by adopting a 4 x 32-bit ring buffer FIFO and adding a pipeline for the conditional branch. We present a detailed comparison of different instruction cache architectures' performance and energy efficiency recently proposed for Parallel Ultra-Low-Power clusters. On average, when executing a set of real-life IoT applications, our two-level cache improves the performance by up to 20% and loses 7% energy efficiency with respect to the private cache. Compared to a shared cache system, it improves performance by up to 17% and keeps the same energy efficiency. In the end, up to 20% timing (maximum frequency) improvement and software control enable the two-level instruction cache with prefetch adapt to various battery-powered usage cases to balance high performance and energy efficiency.

P-SOCRATES: A parallel software framework for time-critical many-core systems

Article in Press, Corrected Proof

A framework for scientific computing with GPUs

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

Actor Kit: Design and Development of an Actor Framework for Swift

Nell'ambito dello sviluppo software, la concorrenza è sempre stata vista come la strada del futuro. Tuttavia, questa è stata spesso ignorata a causa del continuo sviluppo dell'hardware che ha permesso agli sviluppatori di continuare a scrivere software sequenziale senza doversi preoccupare delle performance. In un'era in cui le nuove architetture hardware presentano processori multi-core, tutto questo non è più possibile. L'obiettivo di questa tesi è stato quello di considerare il Modello ad Attori come valida alternativa allo sviluppo di applicazioni in ambito mobile e quindi di progettare, sviluppare e distribuire un nuovo framework sulla base di tale modello. Il lavoro parte quindi da una panoramica di Swift, il nuovo linguaggio di programmazione presentato da Apple al WWDC 2014, in cui vengono analizzati nel dettaglio i meccanismi che abilitano alla concorrenza. Successivamente viene descritto il modello ad attori in termini di: attori, proprietà, comunicazione e sincronizzazione. Segue poi un'analisi delle principali implementazioni di questo modello, tra cui: Scala, Erlang ed Akka; quest'ultimo rappresenta la base su cui è stato ispirato il lavoro di progettazione e sviluppo del framework Actor Kit. Il quarto capitolo descrive tutti i concetti, le idee e i principi su cui il framework Actor Kit è stato progettato e sviluppato. Infine, l'ultimo capitolo presenta l'utilizzo del framework in due casi comuni della programmazione mobile: 1) Acquisizione dati da Web API e visualizzazione sull'interfaccia utente. 2) Acquisizione dati dai sensori del dispositivo. In conclusione Actor Kit abilita la progettazione e lo sviluppo di applicazioni secondo un approccio del tutto nuovo nell'ambito mobile. Un possibile sviluppo futuro potrebbe essere l'estensione del framework con attori che mappino i framework standard di Apple; proprio per questo sarà reso pubblico con la speranza che altri sviluppatori possano evolverlo e renderlo ancora più completo e performante.

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).