On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Temperature management for heterogeneous multi-core FPGAs using adaptive evolutionary multi-objective approaches

Heterogeneous multi-core FPGAs contain different types of cores, which can improve efficiency when used with an effective online task scheduler. However, it is not easy to find the right cores for tasks when there are multiple objectives or dozens of cores. Inappropriate scheduling may cause hot spots which decrease the reliability of the chip. Given that, our research builds a simulating platform to evaluate all kinds of scheduling algorithms on a variety of architectures. On this platform, we provide an online scheduler which uses multi-objective evolutionary algorithm (EA). Comparing the EA and current algorithms such as Predictive Dynamic Thermal Management (PDTM) and Adaptive Temperature Threshold Dynamic Thermal Management (ATDTM), we find some drawbacks in previous work. First, current algorithms are overly dependent on manually set constant parameters. Second, those algorithms neglect optimization for heterogeneous architectures. Third, they use single-objective methods, or use linear weighting method to convert a multi-objective optimization into a single-objective optimization. Unlike other algorithms, the EA is adaptive and does not require resetting parameters when workloads switch from one to another. EAs also improve performance when used on heterogeneous architecture. A efficient Pareto front can be obtained with EAs for the purpose of multiple objectives.

Implementation of X-ray diffraction in the measurement of residual thermal strains

Microelectronic systems are multi-material, multi-layer structures, fabricated and exposed to environmental stresses over a wide range of temperatures. Thermal and residual stresses created by thermal mismatches in films and interconnections are a major cause of failure in microelectronic devices. Due to new device materials, increasing die size and the introduction of new materials for enhanced thermal management, differences in thermal expansions of various packaging materials have become exceedingly important and can no longer be neglected. X-ray diffraction is an analytical method using a monochromatic characteristic X-ray beam to characterize the crystal structure of various materials, by measuring the distances between planes in atomic crystalline lattice structures. As a material is strained, this interplanar spacing is correspondingly altered, and this microscopic strain is used to determine the macroscopic strain. This thesis investigates and describes the theory and implementation of X-ray diffraction in the measurement of residual thermal strains. The design of a computer controlled stress attachment stage fully compatible with an Anton Paar heat stage will be detailed. The stress determined by the diffraction method will be compared with bimetallic strip theory and finite element models.

Advanced thermal analysis of microelectronics using spreading resistance models

Thermal analysis of electronic devices is one of the most important steps for designing of modern devices. Precise thermal analysis is essential for designing an effective thermal management system of modern electronic devices such as batteries, LEDs, microelectronics, ICs, circuit boards, semiconductors and heat spreaders. For having a precise thermal analysis, the temperature profile and thermal spreading resistance of the device should be calculated by considering the geometry, property and boundary conditions. Thermal spreading resistance occurs when heat enters through a portion of a surface and flows by conduction. It is the primary source of thermal resistance when heat flows from a tiny heat source to a thin and wide heat spreader. In this thesis, analytical models for modeling the temperature behavior and thermal resistance in some common geometries of microelectronic devices such as heat channels and heat tubes are investigated. Different boundary conditions for the system are considered. Along the source plane, a combination of discretely specified heat flux, specified temperatures and adiabatic condition are studied. Along the walls of the system, adiabatic or convective cooling boundary conditions are assumed. Along the sink plane, convective cooling with constant or variable heat transfer coefficient are considered. Also, the effect of orthotropic properties is discussed. This thesis contains nine chapters. Chapter one is the introduction and shows the concepts of thermal spreading resistance besides the originality and importance of the work. Chapter two reviews the literatures on the thermal spreading resistance in the past fifty years with a focus on the recent advances. In chapters three and four, thermal resistance of a twodimensional flux channel with non-uniform convection coefficient in the heat sink plane is studied. The non-uniform convection is modeled by using two functions than can simulate a wide variety of different heat sink configurations. In chapter five, a non-symmetrical flux channel with different heat transfer coefficient along the right and left edges and sink plane is analytically modeled. Due to the edge cooling and non-symmetry, the eigenvalues of the system are defined using the heat transfer coefficient on both edges and for satisfying the orthogonality condition, a normalized function is calculated. In chapter six, thermal behavior of two-dimensional rectangular flux channel with arbitrary boundary conditions on the source plane is presented. The boundary condition along the source plane can be a combination of the first kind boundary condition (Dirichlet or prescribed temperature) and the second kind boundary condition (Neumann or prescribed heat flux). The proposed solution can be used for modeling the flux channels with numerous different source plane boundary conditions without any limitations in the number and position of heat sources. In chapter seven, temperature profile of a circular flux tube with discretely specified boundary conditions along the source plane is presented. Also, the effect of orthotropic properties are discussed. In chapter 8, a three-dimensional rectangular flux channel with a non-uniform heat convection along the heat sink plane is analytically modeled. In chapter nine, a summary of the achievements is presented and some systems are proposed for the future studies. It is worth mentioning that all the models and case studies in the thesis are compared with the Finite Element Method (FEM).

Thermal Tracking and Estimation for Microprocessors

Due to increasing integration density and operating frequency of today's high performance processors, the temperature of a typical chip can easily exceed 100 degrees Celsius. However, the runtime thermal state of a chip is very hard to predict and manage due to the random nature in computing workloads, as well as the process, voltage and ambient temperature variability (together called PVT variability). The uneven nature (both in time and space) of the heat dissipation of the chip could lead to severe reliability issues and error-prone chip behavior (e.g. timing errors). Many dynamic power/thermal management techniques have been proposed to address this issue such as dynamic voltage and frequency scaling (DVFS), clock gating and etc. However, most of such techniques require accurate knowledge of the runtime thermal state of the chip to make efficient and effective control decisions. In this work we address the problem of tracking and managing the temperature of microprocessors which include the following sub-problems: (1) how to design an efficient sensor-based thermal tracking system on a given design that could provide accurate real-time temperature feedback; (2) what statistical techniques could be used to estimate the full-chip thermal profile based on very limited (and possibly noise-corrupted) sensor observations; (3) how do we adapt to changes in the underlying system's behavior, since such changes could impact the accuracy of our thermal estimation. The thermal tracking methodology proposed in this work is enabled by on-chip sensors which are already implemented in many modern processors. We first investigate the underlying relationship between heat distribution and power consumption, then we introduce an accurate thermal model for the chip system. Based on this model, we characterize the temperature correlation that exists among different chip modules and explore statistical approaches (such as those based on Kalman filter) that could utilize such correlation to estimate the accurate chip-level thermal profiles in real time. Such estimation is performed based on limited sensor information because sensors are usually resource constrained and noise-corrupted. We also took a further step to extend the standard Kalman filter approach to account for (1) nonlinear effects such as leakage-temperature interdependency and (2) varying statistical characteristics in the underlying system model. The proposed thermal tracking infrastructure and estimation algorithms could consistently generate accurate thermal estimates even when the system is switching among workloads that have very distinct characteristics. Through experiments, our approaches have demonstrated promising results with much higher accuracy compared to existing approaches. Such results can be used to ensure thermal reliability and improve the effectiveness of dynamic thermal management techniques.

Development of a large scale flexible LED display matrix for the screen industry

This project addresses the viability of lightweight, low power consumption, flexible, large format LED screens. The investigation encompasses all aspects of the electrical and mechanical design, individually and as a system, and achieves a successful full scale prototype. The prototype implements novel techniques to achieve large displacement colour aliasing, a purely passive thermal management solution, a rapid deployment system, individual seven bit LED current control with two way display communication, auto-configuration and complete signal redundancy, all of which are in direct response to industry needs.

Temperature monitoring of nonanaesthetised patients in a cardiac catheterisation laboratory

Aim and objectives To identify the prevalence that temperature reduced by more than 1°C from pre to post-procedure in a sample of non-anaesthetised patients undergoing procedures in a cardiac catheterisation laboratory. Background Advances in medical technology are minimising the invasiveness of diagnostic tests and treatments for disease, which is correspondingly increasing the number of medical procedures performed without sedation or anaesthesia. Procedural areas in which medical procedures are performed without anaesthesia are typically kept at a cool temperature for staff comfort. As such, there is a need to inform nursing practices in regard to the thermal management of non-anaesthetised patients undergoing procedures in surgical or procedural environments. Design Single-site observational study Methods Patients were included if they had undergone an elective procedure without sedation or anaesthesia in a cardiac catheterisation laboratory. Ambient room temperature was maintained between 18°C and 20°C. Passive warming with heated cotton blankets was applied. Nurses measured body temperature and thermal comfort before and after 342 procedures. Results Mean change in temperature was -0.08°C (Standard deviation 0.43). The reduction in temperature was more than 1°C after 11 procedures (3.2%). One patient whose temperature had reduced more than 1°C after their procedure reported thermal discomfort. A total of 12 patients were observed to be shivering post-procedure (3.6%). No demographic or clinical characteristics were associated with reduction in temperature of more than 1°C from pre to post-procedure. Conclusions Significant reduction in body temperature was rare in our sample of non-anaesthetised patients. Relevance to clinical practice Similar results would likely be found in other procedural contexts during procedures conducted in settings with comparable room temperatures where passive warming can also be applied with limited skin exposure.

A self-supported 40W direct methanol fuel cell system

A self-supported 40W Direct Methanol Fuel Cell (DMFC) system has been developed and performance tested. The auxiliaries in the DMFC system comprise a methanol sensor, a liquid-level indicator, and fuel and air pumps that consume a total power of about 5W. The system has a 15-cell DMFC stack with active electrode-area of 45 cm(2). The self-supported DMFC system addresses issues related to water recovery from the cathode exhaust, and maintains a constant methanol-feed concentration with thermal management in the system. Pure methanol and water from cathode exhaust are pumped to the methanol-mixing tank where the liquid level is monitored and controlled with the help of a liquid-level indicator. During the operation, methanol concentration in the feed solution at the stack outlet is monitored using a methanol sensor, and pure methanol is added to restore the desired methanol concentration in the feed tank by adding the product water from the cathode exhaust. The feed-rate requirements of fuel and oxidant are designed for the stack capacity of 40W. The self-supported DMFC system is ideally suited for various defense and civil applications and, in particular, for charging the storage batteries.

Performance Analysis of Heat Sinks With Phase-Change Materials Subjected to Transient and Cyclic Heating

Phase-change cooling technique is a suitable method for thermal management of electronic equipment subjected to transient or cyclic heat loads. The thermal performance of a phase-change based heat sink under cyclic heat load depends on several design parameters, namely, applied heat flux, cooling heat transfer coefficient, thermophysical properties of phase-change materials (PCMs), and physical dimensions of phase-change storage system during melting and freezing processes. A one-dimensional conduction heat transfer model is formulated to evaluate the effectiveness of preliminary design of practical PCM-based energy storage units. In this model, the phase-change process of the PCM is divided into melting and solidification subprocesses, for which separate equations are written. The equations are solved sequentially and an explicit closed-form solution is obtained. The efficacy of analytical model is estimated by comparing with a finite-volume-based numerical solution for both transient and cyclic heat loads.

Uniform mems chip temperatures in the nucleate boiling heat transfer region by selecting suitable, medium boiling number range

The not only lower but also uniform MEMS chip temperatures can he reached by selecting suitable boiling number range that ensures the nucleate boiling heat transfer. In this article, boiling heat transfer experiments in 10 silicon triangular microchannels with the hydraulic diameter of 55.4 mu m were performed using acetone as the working fluid, having the inlet liquid temperatures of 24-40 degrees C, mass fluxes of 96-360 kg/m(2)s, heat fluxes of 140-420 kW/m(2), and exit vapor mass qualities of 0.28-0.70. The above data range correspond to the boiling number from 1.574 x 10(-3) to 3.219 x 10(-3) and ensure the perfect nucleate boiling heat transfer region, providing a very uniform chip temperature distribution in both streamline and transverse directions. The boiling heat transfer coefficients determined by the infrared radiator image system were found to he dependent on the heat Axes only, not dependent on the mass Axes and the vapor mass qualities covering the above data range. The high-speed flow visualization shows that the periodic flow patterns take place inside the microchannel in the time scale of milliseconds, consisting of liquid refilling stage, bubble nucleation, growth and coalescence stage, and transient liquid film evaporation stage in a full cycle. The paired or triplet bubble nucleation sites can occur in the microchannel corners anywhere along the flow direction, accounting for the nucleate boiling heat transfer mode. The periodic boiling process is similar to a series of bubble nucleation, growth, and departure followed by the liquid refilling in a single cavity for the pool boiling situation. The chip temperature difference across the whole two-phase area is found to he small in a couple of degrees, providing a better thermal management scheme for the high heat flux electronic components. Chen's [11 widely accepted correlation for macrochannels and Bao et al.'s [21 correlation obtained in a copper capillary tube with the inside diameter of 1.95 mm using R11 and HCFC123 as working fluids can predict the present experimental data with accepted accuracy. Other correlations fail to predict the correct heat transfer coefficient trends. New heat transfer correlations are also recommended.

Optimization and finite element analysis for reliable electronic packaging

This paper demonstrates a modeling and design approach that couples computational mechanics techniques with numerical optimisation and statistical models for virtual prototyping and testing in different application areas concerning reliability of eletronic packages. The integrated software modules provide a design engineer in the electronic manufacturing sector with fast design and process solutions by optimizing key parameters and taking into account complexity of certain operational conditions. The integrated modeling framework is obtained by coupling the multi-phsyics finite element framework - PHYSICA - with the numerical optimisation tool - VisualDOC into a fully automated design tool for solutions of electronic packaging problems. Response Surface Modeling Methodolgy and Design of Experiments statistical tools plus numerical optimisaiton techniques are demonstrated as a part of the modeling framework. Two different problems are discussed and solved using the integrated numerical FEM-Optimisation tool. First, an example of thermal management of an electronic package on a board is illustrated. Location of the device is optimized to ensure reduced junction temperature and stress in the die subject to certain cooling air profile and other heat dissipating active components. In the second example thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and subsequently used to optimise the life-time of solder interconnects under thermal cycling.

Response Surface Modeling and Optimisation for Reliable Electronic Products

The aim of integrating computational mechanics (FEA and CFD) and optimization tools is to speed up dramatically the design process in different application areas concerning reliability in electronic packaging. Design engineers in the electronics manufacturing sector may use these tools to predict key design parameters and configurations (i.e. material properties, product dimensions, design at PCB level. etc) that will guarantee the required product performance. In this paper a modeling strategy coupling computational mechanics techniques with numerical optimization is presented and demonstrated with two problems. The integrated modeling framework is obtained by coupling the multi-physics analysis tool PHYSICA - with the numerical optimization package - Visua/DOC into a fuJly automated design tool for applications in electronic packaging. Thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and life-time under thermal cycling. Also a thermal management design based on multi-physics analysis with coupled thermal-flow-stress modeling is discussed. The Response Surface Modeling Approach in conjunction with Design of Experiments statistical tools is demonstrated and used subsequently by the numerical optimization techniques as a part of this modeling framework. Predictions for reliable electronic assemblies are achieved in an efficient and systematic manner.

Design and modeling challenges for high density packaging

Today most of the IC and board designs are undertaken using two-dimensional graphics tools and rule checks. System-in-package is driving three-dimensional design concepts and this is posing a number of challenges for electronic design automation (EDA) software vendors. System-in-package requires three-dimensional EDA tools and design collaboration systems with appropriate manufacturing and assembly rules for these expanding technologies. Simulation and Analysis tools today focus on one aspect of the design requirement, for example, thermal, electrical or mechanical. System-in-Package requires analysis and simulation tools that can easily capture the complex three dimensional structures and provided integrated fast solutions to issues such as thermal management, reliability, electromagnetic interference, etc. This paper discusses some of the challenges faced by the design and analysis community in providing appropriate tools to engineers for System-in-Package design

Numerically Investigating the Effects of Cross-Links in Scaled Microchannel Heat Sinks

Thermal management as a method of heightening performance in miniaturized electronic devices using microchannel heat sinks has recently become of interest to researchers and the industry. One of the current challenges is to design heat sinks with uniform flow distribution. A number of experimental studies have been conducted to seek appropriate designs for microchannel heat sinks. However, pursuing this goal experimentally can be an expensive endeavor. The present work investigates the effect of cross-links on adiabatic two-phase flow in an array of parallel channels. It is carried out using the three dimensional mixture model from the computational fluid dynamics software, FLUENT 6.3. A straight channel and two cross-linked channel models were simulated. The cross-links were located at 1/3 and 2/3 of the channel length, and their widths were one and two times larger than the channel width. All test models had 45 parallel rectangular channels, with a hydraulic diameter of 1.59 mm. The results showed that the trend of flow distribution agrees with experimental results. A new design, with cross-links incorporated, was proposed and the results showed a significant improvement of up to 55% on flow distribution compared with the standard straight channel configuration without a penalty in the pressure drop. Further discussion about the effect of cross-links on flow distribution, flow structure, and pressure drop was also documented.

Mathematical Modelling of a Reciprocating Piston Expander

Modern internal combustion (IC) engines reject around two thirds of the energy provided by the fuel as low-grade waste heat. Capturing a portion of this waste heat energy and transforming it into a more useful form of energy could result in a significant reduction in fuel consumption. By using the low-grade heat, an organic Rankine cycle (ORC) can produce mechanical work from a pressurised organic fluid with the use of an expander.
Ideal gas assumptions are shown to produce significant errors in expander performance predictions when using an organic fluid. This paper details the mathematical modelling technique used to accurately model the thermodynamic processes for both ideal and non-ideal fluids within the reciprocating expander. A comparison between the two methods illustrates the extent of the errors when modelling a reciprocating piston expander. Use of the ideal gas assumptions are shown to produce an error of 55% in the prediction of power produced by the expander when operating on refrigerant R134a.