Low-power vertical cavity NAND gate

The study of the Vertical-Cavity Semiconductor Optical Amplifiers (VCSOAs) for optical signal processing applications is increasing his interest. Due to their particular structure, the VCSOAs present some advantages when compared to their edge-emitting counterparts including low manufacturing costs, high coupling efficiency to optical fibers and the ease to fabricate 2-D arrays of this kind of devices. As a consequence, all-optical logic gates based on VCSOAs may be very promising devices for their use in optical computing and optical switching in communications. Moreover, since all the boolean logic functions can be implemented by combining NAND logic gates, the development of a Vertical-Cavity NAND gate would be of particular interest. In this paper, the characteristics of the dispersive optical bistability appearing on a VCSOA operated in reflection are studied. A progressive increment of the number of layers compounding the top Distributed Bragg Reflector (DBR) of the VCSOA results on a change on the shape of the appearing bistability from an S-shape to a clockwise bistable loop. This resulting clockwise bistability has high on-off contrast ratio and input power requirements one order of magnitude lower than those needed for edge-emitting devices. Based on these results, an all-optical vertical-cavity NAND gate with high on-off contrast ratio and an input power for operation of only 10|i\V will be reported in this paper.

Quantum computation with coupled quantum dots embedded in optical microcavities

Based on an idea that spatial separation of charge states can enhance quantum coherence, we propose a scheme for a quantum computation with the quantum bit (qubit) constructed from two coupled quantum dots. Quantum information is stored in the electron-hole pair state with the electron and hole located in different dots, which enables the qubit state to be very long-lived. Universal quantum gates involving any pair of qubits are realized by coupling the quantum dots through the cavity photon which is a hopeful candidate for the transfer of long-range information. The operation analysis is carried out by estimating the gate time versus the decoherence time.

Use of semiconductor optical amplifiers in signal processing applications

We describe a 42.6 Gbit/s all-optical pattern recognition system which uses semiconductor optical amplifiers (SOAs). A circuit with three SOA-based logic gates is used to identify the presence of specific port numbers in an optical packet header.

Multiply reconfigurable ‘plug and play’ molecular logic via self-assembly

A substantial set of ion-driven molecular logic gates are implemented in turn by arranging the association between easily available lumophores and receptors in detergent micelles.

Experimental Investigation of Three-Dimensional Single and Double optical Lattices

A complete laser cooling setup was built, with focus on threedimensional near-resonant optical lattices for cesium. These consist of regularly ordered micropotentials, created by the interference of four laser beams. One key feature of optical lattices is an inherent ”Sisyphus cooling” process. It efficiently extracts kinetic energy from the atoms, leading to equilibrium temperatures of a few µK. The corresponding kinetic energy is lower than the depth of the potential wells, so that atoms can be trapped. We performed detailed studies of the cooling processes in optical lattices by using the time-of-flight and absorption-imaging techniques. We investigated the dependence of the equilibrium temperature on the optical lattice parameters, such as detuning, optical potential and lattice geometry. The presence of neighbouring transitions in the cesium hyperfine level structure was used to break symmetries in order to identify, which role “red” and “blue” transitions play in the cooling. We also examined the limits for the cooling process in optical lattices, and the possible difference in steady-state velocity distributions for different directions. Moreover, in collaboration with ´Ecole Normale Sup´erieure in Paris, numerical simulations were performed in order to get more insight in the cooling dynamics of optical lattices. Optical lattices can keep atoms almost perfectly isolated from the environment and have therefore been suggested as a platform for a host of possible experiments aimed at coherent quantum manipulations, such as spin-squeezing and the implementation of quantum logic-gates. We developed a novel way to trap two different cesium ground states in two distinct, interpenetrating optical lattices, and to change the distance between sites of one lattice relative to sites of the other lattice. This is a first step towards the implementation of quantum simulation schemes in optical lattices.

Improved design of all-optical processor for modular arithmetic

A new improved design of an all-optical processor that performs modular arithmetic is presented. The modulo-processor is based on all-optical circuit of interconnected semiconductor optical amplifier logic gates. The design allows processing times of less than 1 µs for 16-bit operation at 10 Gb/s and up to 32-bit operation at 100 Gb/s.

Design of fast core node processor for packet forwarding without header modification in optical networks

We present a design of a fast all-optical core-node processor that performs packet-forwarding in optical networks without header-modification. The design is based on bit-serial architecture using TOADs as logic-gates that perform modulo-arithmetic to forward packets.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Parallel optical negabinary signed-digit computing: algorithm and optical implementation

Negabinary is a component of the positional number system. A complete set of negabinary arithmetic operations are presented, including the basic addition/subtraction logic, the two-step carry-free addition/subtraction algorithm based on negabinary signed-digit (NSD) representation, parallel multiplication, and the fast conversion from NSD to the normal negabinary in the carry-look-ahead mode. All the arithmetic operations can be performed with binary logic. By programming the binary reference bits, addition and subtraction can be realized in parallel with the same binary logic functions. This offers a technique to perform space-variant arithmetic-logic functions with space-invariant instructions. Multiplication can be performed in the tree structure and it is simpler than the modified signed-digit (MSD) counterpart. The parallelism of the algorithms is very suitable for optical implementation. Correspondingly, a general-purpose optical logic system using an electron trapping device is suggested. Various complex logic functions can be performed by programming the illumination of the data arrays without additional temporal latency of the intermediate results. The system can be compact. These properties make the proposed negabinary arithmetic-logic system a strong candidate for future applications in digital optical computing with the development of smart pixel arrays. (C) 1999 Society of Photo-Optical Instrumentation Engineers. [S0091-3286(99)00803-X].

Luminescent Photoinduced Electron Transfer (PET) Molecules for Sensing and Logic Operations

Chemical species can serve as inputs to supramolecular devices so that a luminescence output is created in a conditional manner. Conditionality is built into these devices by employing the classical photochemical process of photoinduced electron transfer (PET) to compete with luminescence emission. The response of these devices in the analogue regime leads to sensors that can operate in nanometric, micrometric, and millimetric spaces. Some of these devices serve in membrane science, cell physiology, and medical diagnostics. The response in the digital regime leads to Boolean logic gates. Some of these find application in improving aspects of medical diagnostics and in identifying small objects in large populations.

Molecular Logic Gate Arrays

Chemists are now able to emulate the ideas and instruments of mathematics and computer science with molecules. The integration of molecular logic gates into small arrays has been a growth area during the last few years. The design principles underlying a collection of these cases are examined. Some of these computing molecules are applicable in medical- and biotechnologies. Cases of blood diagnostics, 'lab-on-a-molecule' systems, and molecular computational identification of small objects are included.

Switching between molecular switch types by module rearrangement:Ca -enabled, H-driven 'off-on-off', H-driven YES and PASS 0 as well as H, Ca-driven AND logic operations

Several logic gates and switches can be accessed from two different combinations of a single set of fluorophore, receptor and spacer components.

A Coordination and Ligand Replacement Based Three-Input Colorimetric Logic Gate Sensing Platform for Melamine, Mercury Ions, and Cysteine

Discrimination of different species in various target scopes within a single sensing platform can provide many advantages such as simplicity, rapidness, and cost effectiveness. Here we design a three-input colorimetric logic gate based on the aggregation and anti-aggregation of gold nanoparticles (Au NPs) for the sensing of melamine, cysteine, and Hg2+. The concept takes advantages of the highly specific coordination and ligand replacement reactions between melamine, cysteine, Hg2+, and Au NPs. Different outputs are obtained with the combinational inputs in the logic gates, which can serve as a reference to discriminate different analytes within a single sensing platform. Furthermore, besides the intrinsic sensitivity and selectivity of Au NPs to melamine-like compounds, the “INH” gates of melamine/cysteine and melamine/Hg2+ in this logic system can be employed for sensitive and selective detections of cysteine and Hg2+, respectively.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.