Integration of silicon plasmonic schottky photodetector for on chip signal tapping at telecom wavelengths

We experimentally demonstrate the use of an on-chip integrated Schottky plasmonic detector for testing, monitoring and tapping signals in plasmonic and photonic devices. Theoretical model and measurement of external and integrated devices will be presented. © OSA 2013.

Integration of silicon plasmonic schottky photodetector for on chip signal tapping at telecom wavelengths

We experimentally demonstrate the use of an on-chip integrated Schottky plasmonic detector for testing, monitoring and tapping signals in plasmonic and photonic devices. Theoretical model and measurement of external and integrated devices will be presented. © OSA 2013.

Integration of silicon plasmonic schottky photodetector for on chip signal tapping at telecom wavelengths

We experimentally demonstrate the use of an on-chip integrated Schottky plasmonic detector for testing, monitoring and tapping signals in plasmonic and photonic devices. Theoretical model and measurement of external and integrated devices will be presented. © OSA 2013.

On chip plasmonic enhanced silicon Schottky detector for telecom wavelengths

We demonstrate an integrated on-chip plasmonic enhanced Schottky detector for telecom wavelengths based on the internal photoemission process. This CMOS compatible device may serve as a promising alternative to the Si-Ge detectors. © 2012 OSA.

Plasmonic nanotips for on-chip nanoscale confinement of light

We demonstrate the on-chip nanoscale focusing of surface plasmons in metallic nanotip coupled to the silicon waveguide. Strong field enhancement is observed at the apex of the tip. Enhancing light matter interactions is discussed. © 2012 OSA.

Plasmonic nanotips for on-chip focusing of light

We investigate numerically and experimentally the on-chip nanoscale focusing of surface plasmon polaritons (SPPs) in metallic nanotip coupled to the silicon waveguide. Strong field enhancement is observed at the apex of the tip. © 2011 IEEE.

On-chip focusing of light by metallic nanotip

We present a numerical simulations, fabrication and experimental results for on-chip focusing of surface plasmon polaritons (SPPs) in metal nanotip coupled to the silicon waveguide © 2011 OSA.

Plasmonic nanotips for on-chip nanoscale confinement of light

We demonstrate the on-chip nanoscale focusing of surface plasmons in metallic nanotip coupled to the silicon waveguide. Strong field enhancement is observed at the apex of the tip. Enhancing light matter interactions is discussed. © 2011 Optical Society of America.

On chip plasmonic enhanced silicon schottky detector for telecom wavelengths

We demonstrate an integrated on-chip plasmonic enhanced Schottky detector for telecom wavelengths based on the internal photoemission process. This CMOS compatible device may serve as a promising alternative to the Si-Ge detectors. © 2011 Optical Society of America.

On-chip focusing of light by metallic nanotip

We present a numerical simulations, fabrication and experimental results for on-chip focusing of surface plasmon polaritons (SPPs) in metal nanotip coupled to the silicon waveguide. © 2011 Optical Society of America.

On-chip tunable micro-ring resonator based on digital microfluidics platform

We demonstrate the tunability of a silicon nitride micro-resonator using the concept of Digital Microfluidics. Our system allows driving micro-droplets on-chip, enabling the control of the effective refractive index at the vicinity of the resonator. © 2010 OSA/FiO/LS 2010.

On-chip focusing of light by Metallic Nanotip

We investigate numerically and experimentally the on-chip nanoscale focusing of surface plasmon polaritons (SPPs) in metallic nanotip coupled to the silicon waveguide. Strong field enhancement is observed at the apex of the tip. © 2010 Optical Society of America.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.