Exploration of RVC applications using an ARM multicore processor = Exploración de aplicaciones RVC empleando un procesador ARM multinúcleo

Single core capabilities have reached their maximum clock speed; new multicore architectures provide an alternative way to tackle this issue instead. The design of decoding applications running on top of these multicore platforms and their optimization to exploit all system computational power is crucial to obtain best results. Since the development at the integration level of printed circuit boards are increasingly difficult to optimize due to physical constraints and the inherent increase in power consumption, development of multiprocessor architectures is becoming the new Holy Grail. In this sense, it is crucial to develop applications that can run on the new multi-core architectures and find out distributions to maximize the potential use of the system. Today most of commercial electronic devices, available in the market, are composed of embedded systems. These devices incorporate recently multi-core processors. Task management onto multiple core/processors is not a trivial issue, and a good task/actor scheduling can yield to significant improvements in terms of efficiency gains and also processor power consumption. Scheduling of data flows between the actors that implement the applications aims to harness multi-core architectures to more types of applications, with an explicit expression of parallelism into the application. On the other hand, the recent development of the MPEG Reconfigurable Video Coding (RVC) standard allows the reconfiguration of the video decoders. RVC is a flexible standard compatible with MPEG developed codecs, making it the ideal tool to integrate into the new multimedia terminals to decode video sequences. With the new versions of the Open RVC-CAL Compiler (Orcc), a static mapping of the actors that implement the functionality of the application can be done once the application executable has been generated. This static mapping must be done for each of the different cores available on the working platform. It has been chosen an embedded system with a processor with two ARMv7 cores. This platform allows us to obtain the desired tests, get as much improvement results from the execution on a single core, and contrast both with a PC-based multiprocessor system. Las posibilidades ofrecidas por el aumento de la velocidad de la frecuencia de reloj de sistemas de un solo procesador están siendo agotadas. Las nuevas arquitecturas multiprocesador proporcionan una vía de desarrollo alternativa en este sentido. El diseño y optimización de aplicaciones de descodificación de video que se ejecuten sobre las nuevas arquitecturas permiten un mejor aprovechamiento y favorecen la obtención de mayores rendimientos. Hoy en día muchos de los dispositivos comerciales que se están lanzando al mercado están integrados por sistemas embebidos, que recientemente están basados en arquitecturas multinúcleo. El manejo de las tareas de ejecución sobre este tipo de arquitecturas no es una tarea trivial, y una buena planificación de los actores que implementan las funcionalidades puede proporcionar importantes mejoras en términos de eficiencia en el uso de la capacidad de los procesadores y, por ende, del consumo de energía. Por otro lado, el reciente desarrollo del estándar de Codificación de Video Reconfigurable (RVC), permite la reconfiguración de los descodificadores de video. RVC es un estándar flexible y compatible con anteriores codecs desarrollados por MPEG. Esto hace de RVC el estándar ideal para ser incorporado en los nuevos terminales multimedia que se están comercializando. Con el desarrollo de las nuevas versiones del compilador específico para el desarrollo de lenguaje RVC-CAL (Orcc), en el que se basa MPEG RVC, el mapeo estático, para entornos basados en multiprocesador, de los actores que integran un descodificador es posible. Se ha elegido un sistema embebido con un procesador con dos núcleos ARMv7. Esta plataforma nos permitirá llevar a cabo las pruebas de verificación y contraste de los conceptos estudiados en este trabajo, en el sentido del desarrollo de descodificadores de video basados en MPEG RVC y del estudio de la planificación y mapeo estático de los mismos.

MultiPARTES: Multicore Virtualization for Mixed-Criticality Systems

Modern embedded applications typically integrate a multitude of functionalities with potentially different criticality levels into a single system. Without appropriate preconditions, the integration of mixed-criticality subsystems can lead to a significant and potentially unacceptable increase of engineering and certification costs. A promising solution is to incorporate mechanisms that establish multiple partitions with strict temporal and spatial separation between the individual partitions. In this approach, subsystems with different levels of criticality can be placed in different partitions and can be verified and validated in isolation. The MultiPARTES FP7 project aims at supporting mixed- criticality integration for embedded systems based on virtualization techniques for heterogeneous multicore processors. A major outcome of the project is the MultiPARTES XtratuM, an open source hypervisor designed as a generic virtualization layer for heterogeneous multicore. MultiPARTES evaluates the developed technology through selected use cases from the offshore wind power, space, visual surveillance, and automotive domains. The impact of MultiPARTES on the targeted domains will be also discussed. In a number of ongoing research initiatives (e.g., RECOMP, ARAMIS, MultiPARTES, CERTAINTY) mixed-criticality integration is considered in multicore processors. Key challenges are the combination of software virtualization and hardware segregation and the extension of partitioning mechanisms to jointly address significant non-functional requirements (e.g., time, energy and power budgets, adaptivity, reliability, safety, security, volume, weight, etc.) along with development and certification methodology.

On real-time partitioned multicore systems

Partitioning is a common approach to developing mixed-criticality systems, where partitions are isolated from each other both in the temporal and the spatial domain in order to prevent low-criticality subsystems from compromising other subsystems with high level of criticality in case of misbehaviour. The advent of many-core processors, on the other hand, opens the way to highly parallel systems in which all partitions can be allocated to dedicated processor cores. This trend will simplify processor scheduling, although other issues such as mutual interference in the temporal domain may arise as a consequence of memory and device sharing. The paper describes an architecture for multi-core partitioned systems including critical subsystems built with the Ada Ravenscar profile. Some implementation issues are discussed, and experience on implementing the ORK kernel on the XtratuM partitioning hypervisor is presented.

Forward micro-inverter with primary-parallel secondary-series multicore transformer

This paper presents a primary-parallel secondary-series multicore forward micro-inverter for photovoltaic AC-module application. The proposed solution changes the number of active phases depending on the grid voltage, thus enabling the usage of low-profile unitary turns ratio transformers. Therefore, the transformers are well coupled and the overall performance of the inverter is improved. Due to the multiphase solution the number of devices increases but, the current stress and losses per device are reduced contributing to an easier thermal management. Furthermore, the decoupling capacitor is split between the phases, contributing to a low-profile solution without electrolytic capacitors suitable to be mounted in the frame of a PV module.

Aceleración de Algoritmos en Procesadores Multicore, GPGPU y FPGA

El avance en la potencia de cómputo en nuestros días viene dado por la paralelización del procesamiento, dadas las características que disponen las nuevas arquitecturas de hardware. Utilizar convenientemente este hardware impacta en la aceleración de los algoritmos en ejecución (programas). Sin embargo, convertir de forma adecuada el algoritmo en su forma paralela es complejo, y a su vez, esta forma, es específica para cada tipo de hardware paralelo. En la actualidad los procesadores de uso general más comunes son los multicore, procesadores paralelos, también denominados Symmetric Multi-Processors (SMP). Hoy en día es difícil hallar un procesador para computadoras de escritorio que no tengan algún tipo de paralelismo del caracterizado por los SMP, siendo la tendencia de desarrollo, que cada día nos encontremos con procesadores con mayor numero de cores disponibles. Por otro lado, los dispositivos de procesamiento de video (Graphics Processor Units - GPU), a su vez, han ido desarrollando su potencia de cómputo por medio de disponer de múltiples unidades de procesamiento dentro de su composición electrónica, a tal punto que en la actualidad no es difícil encontrar placas de GPU con capacidad de 200 a 400 hilos de procesamiento paralelo. Estos procesadores son muy veloces y específicos para la tarea que fueron desarrollados, principalmente el procesamiento de video. Sin embargo, como este tipo de procesadores tiene muchos puntos en común con el procesamiento científico, estos dispositivos han ido reorientándose con el nombre de General Processing Graphics Processor Unit (GPGPU). A diferencia de los procesadores SMP señalados anteriormente, las GPGPU no son de propósito general y tienen sus complicaciones para uso general debido al límite en la cantidad de memoria que cada placa puede disponer y al tipo de procesamiento paralelo que debe realizar para poder ser productiva su utilización. Los dispositivos de lógica programable, FPGA, son dispositivos capaces de realizar grandes cantidades de operaciones en paralelo, por lo que pueden ser usados para la implementación de algoritmos específicos, aprovechando el paralelismo que estas ofrecen. Su inconveniente viene derivado de la complejidad para la programación y el testing del algoritmo instanciado en el dispositivo. Ante esta diversidad de procesadores paralelos, el objetivo de nuestro trabajo está enfocado en analizar las características especificas que cada uno de estos tienen, y su impacto en la estructura de los algoritmos para que su utilización pueda obtener rendimientos de procesamiento acordes al número de recursos utilizados y combinarlos de forma tal que su complementación sea benéfica. Específicamente, partiendo desde las características del hardware, determinar las propiedades que el algoritmo paralelo debe tener para poder ser acelerado. Las características de los algoritmos paralelos determinará a su vez cuál de estos nuevos tipos de hardware son los mas adecuados para su instanciación. En particular serán tenidos en cuenta el nivel de dependencia de datos, la necesidad de realizar sincronizaciones durante el procesamiento paralelo, el tamaño de datos a procesar y la complejidad de la programación paralela en cada tipo de hardware.

Optimización de Base de Datos sobre un cluster de computadoras multicore

La dirección ha desarrollado en los últimos anos un proyecto para la generación de una base de datos con los datos pluviométricos de la provincia, desde 1940 a la actualidad. Para su consulta se diseno una interface tipo web . Dicha base se encuentra cargada en una computadora tipo PC, pero su volumen es tal que el procesamiento requerido para obtener respuestas de consultas particulares o bien de generación de estadísticas, es inaceptable por lo lento. En virtud de esto se hace necesario el traslado de la base a un entorno de mayor capacidad de procesamiento, que en la actualidad, por una cuestion económica, es conveniente hacer sobre un cluster de computadoras multicore, con capacidad de almacenamiento y procesamiento distribuido. Por lo que el objeto de la transferencia es el conocimiento y procedimiento necesario para trasladar a dicho entorno, el estado actual de la base de datos, y su posterior mantenimiento, puesta a punto y optimización del sistema necesario.

Two-axis temperature-insensitive accelerometer based on multicore fiber Bragg gratings

We report a compact two-dimensional accelerometer based upon a simple fiber cantilever constructed from a short length of multicore optical fiber. Two-axis measurement is demonstrated up to 3 kHz. Differential measurement between fiber Bragg gratings written in the multicore fiber provides temperature- insensitive measurements.

Two-axis accelerometer based on multicore fibre Bragg gratings

We report an accelerometer based upon a simple fibre cantilever constructed from a short length of multicore fibre(MCF) containing fibre Bragg gratings (FBGs). Two-axis measurement is demonstrated up to 3 kHz.

Radial deformation measurement of a cylinder under compression using multicore fibre

A multicore fibre (MCF) sensor to measure the radial deformation of a compliant cylinder under compression is presented. The sensor is connectorised and need not be permanently bonded to the test object. A differential measurement technique using FBGs written into the MCF makes the sensor temperature insensitive. FBG measurement of axial strain of a cylinder under compression is also reported.

Tunnel monitoring using multicore displacement sensor

In this paper, we report the first demonstration of multiplexed fibre Bragg grating strain sensors in a multicore fibre for shape measurement and their application to structural monitoring. Sets of gratings, acting as strain gauges, are co-located in the multicore fibre such that they enable the curvature to be determined via differential strain measurement. Multiple sets of these gratings allow the curvature to be measured at several points along the fibre. In this paper, the multicore fibre is configured to measure the deflection of a simple mechanical beam arising from the displacement of concrete tunnel sections. Laboratory tests are presented in which the system was demonstrated capable of displacement measurement with a resolution of ±0.1 mm over a range of several millimetres. © 2006 IOP Publishing Ltd.

Dynamic two-axis curvature measurement using multicore fiber Bragg gratings interrogated by arrayed waveguide gratings

We describe the use of arrayed waveguide gratings (AWGs) in the interrogation of fiber Bragg gratings (FBGs) for dynamic strain measurement. The ratiometric AWG output was calibrated in a static deflection experiment over a ±200 με range. Dynamic strain measurement was demonstrated with a FBG in a conventional single-mode fiber mounted on the surface of a vibrating cantilever and on a piezoelectric actuator, giving a resolution of 0.5 με at 2.4 kHz. We present results of this technique extended to measure the dynamic differential strain between two FBG pairs within a multicore fiber. An arbitrary cantilever oscillation of the multicore fiber was determined from curvature measurements in two orthogonal axes at 1125 Hz with a resolution of 0.05 m-1. © 2006 Optical Society of America.

Transverse load and orientation measurement with multicore fiber Bragg gratings

We demonstrate the sensitivity of Bragg gratings in a multicore fiber to transverse load. The Bragg peaks are split because of stress-induced birefringence, the magnitude of which depends upon the load and grating position relative to the load axis. Experiments show that a set of gratings in a four-core fiber can measure a load axis angle to ±5° and a load magnitude to ±15 N m-1 up to 2500 N m-1. We consider alternative designs of multicore fiber for optimal load sensing and compare experimental and modeled data. © 2005 Optical Society of America.

Pitch and roll sensing using fibre Bragg gratings in multicore fibre

We report the first use of a multicore fibre incorporating fibre Bragg grating strain sensors in each core as a fibre optic pitch and roll sensor. A length of four-core fibre supported at one end forms a cantilever. The differential strains between opposite grating pairs depend on the fibre’s orientation in pitch (in the vertical plane) and roll (azimuth) with respect to gravity. Resolutions of ±2◦ in roll and ±15◦ in pitch were measured.

Power-controlled phase-matching and instability of CW propagation in multicore optical fibers with a central core

We present modulation instability analysis including azimuthal perturbations of steady-state continuous wave (CW) propagation in multicore-fiber configurations with a central core. In systems with a central core, a steady CW evolution regime requires power-controlled phase matching, which offers interesting spatial-division applications. Our results have general applicability and are relevant to a range of physical and engineering systems, including high-power fiber lasers, optical transmission in multicore fiber, and systems of coupled nonlinear waveguides. © 2013 Optical Society of America.