Leakage Temperature Dependency Aware Real-Time Scheduling for Power and Thermal Optimization

Catering to society’s demand for high performance computing, billions of transistors are now integrated on IC chips to deliver unprecedented performances. With increasing transistor density, the power consumption/density is growing exponentially. The increasing power consumption directly translates to the high chip temperature, which not only raises the packaging/cooling costs, but also degrades the performance/reliability and life span of the computing systems. Moreover, high chip temperature also greatly increases the leakage power consumption, which is becoming more and more significant with the continuous scaling of the transistor size. As the semiconductor industry continues to evolve, power and thermal challenges have become the most critical challenges in the design of new generations of computing systems. In this dissertation, we addressed the power/thermal issues from the system-level perspective. Specifically, we sought to employ real-time scheduling methods to optimize the power/thermal efficiency of the real-time computing systems, with leakage/ temperature dependency taken into consideration. In our research, we first explored the fundamental principles on how to employ dynamic voltage scaling (DVS) techniques to reduce the peak operating temperature when running a real-time application on a single core platform. We further proposed a novel real-time scheduling method, “M-Oscillations” to reduce the peak temperature when scheduling a hard real-time periodic task set. We also developed three checking methods to guarantee the feasibility of a periodic real-time schedule under peak temperature constraint. We further extended our research from single core platform to multi-core platform. We investigated the energy estimation problem on the multi-core platforms and developed a light weight and accurate method to calculate the energy consumption for a given voltage schedule on a multi-core platform. Finally, we concluded the dissertation with elaborated discussions of future extensions of our research.

Embedded DSP-Based Compact Fuzzy System and Its Application for Induction-Motor V/f Speed Control

This paper presents a compact embedded fuzzy system for three-phase induction-motor scalar speed control. The control strategy consists in keeping constant the voltage-frequency ratio of the induction-motor supply source. A fuzzy-control system is built on a digital signal processor, which uses speed error and speed-error variation to change both the fundamental voltage amplitude and frequency of a sinusoidal pulsewidth modulation inverter. An alternative optimized method for embedded fuzzy-system design is also proposed. The controller performance, in relation to reference and load-torque variations, is evaluated by experimental results. A comparative analysis with conventional proportional-integral controller is also achieved.

Robust STATCOM control for the stabilisation of fixed-speed wind turbines during low voltages

This paper presents a robust voltage control scheme for fixed-speed wind generators using a static synchronous compensator (STATCOM) controller. To enable a linear and robust control framework with structured uncertainty, the overall system is represented by a linear part plus a nonlinear part that covers an operating range of interest required to ensure stability during severe low voltages. The proposed methodology is flexible and readily applicable to larger wind farms of different configurations. The performance of the control strategy is demonstrated on a two area test system. Large disturbance simulations demonstrate that the proposed controller enhances voltage stability as well as transient stability of induction generators during low voltage ride through (LVRT) transients and thus enhances the LVRT capability. (C) 2011 Elsevier Ltd. All rights reserved.

Technology assessment for power quality mitigation devices - Micro-DVR case study

This work presents a case study on technology assessment for power quality improvement devices. A system compatibility test protocol for power quality mitigation devices was developed in order to evaluate the functionality of three-phase voltage restoration devices. In order to validate this test protocol, the micro-DVR, a reduced power development platform for DVR (dynamic voltage restorer) devices, was tested and the results are discussed based on voltage disturbances standards. (C) 2011 Elsevier B.V. All rights reserved.

Moniensiöinen muuntaja taajuudenmuuttajakäytössä

Suuritehoisissa pumppu- ja puhallinkäytöissä käytetään usein suurnopeusmoottoria,jota syötetään välijännitteellä. Suurjännitetaajuudenmuuttajat ovat kalliita, eikä niitä ole aina edes mahdollista valmistaa. Tutkimuksen kohteena on rinnakkaisilla pienjännitetaajuudenmuuttajilla toteutettu sähkökäyttö, jossa pienjännite nostetaan moniensiöisellä muuntajalla suurjännitteeksi (6,6 kV) ja syötetään edelleen kuormana olevalle suurnopeusmoottorille. Opinnäytetyössä tutkitaan moniensiöisen muuntajan syöttöä rinnakkaisilla taajuudenmuuttajilla sekä niiden aiheuttamia häiriöitä toisilleen. Työssä tutkitaan myös harmonisten yliaaltojen vaikutuksia muuntajan häviöihin ja magnetointiominaisuuksiin. Taajuudenmuuttajan lähtöjännite ja -virta suodatetaan sinisuotimella, jonka parametreja simuloidaan Simulink- ohjelmistolla. Tavoite on löytää optimaaliset parametrit taajuudenmuuttajanlähtösuotimelle käyrämuotojen ja suotimeen jäävän tehon suhteen. Työssä tarkasteltiin sinisuodinta, johon jää 3 prosenttia syöttöjännitteestä. LC-suodin kompensoi sähkökäytön loistehon lähes kokonaan, joten taajuudenmuuttajien antotehon kannalta suotimet ovat perusteltuja. Taajuudenmuuttajan näennäisteho putoaa 22 prosenttia, joten taajuudenmuuttajat voidaan vastaavasti mitoittaa pienemmiksi.

Invertteripääteasteen suunnittelu

Invertteritekniikalla voidaan toteuttaa nykyaikainen, monipuolinen ja tehokas pääteaste moneen eri käyttötarkoitukseen. Tässä työssä suunnitellaan invertteripääteaste mittalaite- ja virtalähdesovelluksiin. Suunnittelussa otetaan huomioon muunneltavuus, valmistuskustannukset ja mitat. Näiden kriteerien lisäksi pääteaste suunnitellaan niin, että se täyttää mittalaite- ja virtalähdesovelluksien vaatimat standardit. Pääteasteen teho rajoittuu 500 VA:iin, mutta vaatimukset lähtöjännitteen erimuotoisuudelle aiheuttavat suunnittelulle omat vaikeutensa. Työssä täytyy tutkia, minkälainen tuloaste, invertteri, suodin ja lähtöaste sopivat parhaiten pääteasteen toteutukseen. Sopivien topologioiden löydyttyä pääteaste simuloidaan tietokoneella, jonka jälkeen voidaan suunnitella prototyyppi käytännön testauksia varten. Suunnittelussa päädyttiin seuraaviin topologioihin: Tuloasteeksi valittiin PFC-piiri, joka on nykyaikana pakollinen invertterikäytössä, koska verkkoon palaavat harmoniset yliaaltokomponentit täytyy suodattaa. Invertteritopologiaksi valittiin kokosiltainvertteri, jolla saadaan parhaiten muutettua lähtöjännitteen taajuutta ja amplitudia. Suodintopologiaksi valittiin LC-suodin, jolla saadaan tehokkaasti suodatettua invertterin aiheuttamat harmoniset yliaallot. Lähtöön sijoitetaan muuntaja, jonka muuntosuhdetta muuntamalla saadaan lähtöjännite halutuksi eri käyttötarkoituksia varten.

Servo drive in hoist application

The objective of this master thesis is to test according to hoisting requirements, a servo drive system and compare its performance with the performance of a drive equipped with a vector controlled frequency converter. Both systems utilize closed-loop vector control based on PCL program control. In order to compare the results of tests both systems were connected to the same motor driving a variable speed electrical chain hoist. Tests were based on requirements to both systems. As requirements of tests zero speed operation, operation in field weakening, positioning accuracy and smoothness of motion are taken into consideration. Both systems demonstrate quite similar performance and meet the requirements. Servo drive system demonstrates a high positioning accuracy and dynamic performance. Frequency converter is not able to provide the same positioning accuracy and dynamic performance as servo drive.

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.

Virtual Runtime Application Partitions for Resource Management in Massively Parallel Architectures

This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.

Desenho e Construção de um protótipo gerador de jato de plasma frio a pressão atmosférica para aplicações biomédicas

Research for better performance materials in biomedical applications are constants. Thus recent studies aimed at the development of new techniques for modification of surfaces. The low pressure plasma has been highlighted for its versatility and for being environmentally friendly, achieving good results in the modification of physic chemical properties of materials. However, it is requires an expensive vacuum system and cannot able to generate superficial changes in specific regions. Furthermore, it is limits their use in polymeric materials and sensitive terms due to high process temperatures. Therefore, new techniques capable of generating cold plasma at atmospheric pressure (APPJ) were created. In order to perform surface treatments on biomaterials in specific regions was built a prototype capable of generating a cold plasma jet. The prototype plasma generator consists of a high voltage source, a support arm, sample port and a nozzle through which the ionized argon. The device was formed to a dielectric tube and two electrodes. This work was varied some parameters such as position between electrodes, voltage and electrical frequency to verify the behavior of glow discharges. The disc of titanium was polished and there was a surface modification. The power consumed, length, intensity and surface modifications of titanium were analyzed. The energy consumed during the discharges was observed by the Lissajous figure method. To check the length of the jets was realized with Image Pro Plus software. The modifications of the titanium surfaces were observed by optical microscopy (OM ) and atomic force microscopy (AFM ). The study showed that variations of the parameters such as voltage, frequency and geometric position between the electrodes influence the formation of the plasma jet. It was concluded that the plasma jet near room temperature and atmospheric pressure was able to cause modifications in titanium surface

Technology assessment for power quality mitigation devices - Micro-DVR case study

This work presents a case study on technology assessment for power quality improvement devices. A system compatibility test protocol for power quality mitigation devices was developed in order to evaluate the functionality of three-phase voltage restoration devices. In order to validate this test protocol, the micro-DVR, a reduced power development platform for DVR (dynamic voltage restorer) devices, was tested and the results are discussed based on voltage disturbances standards. (C) 2011 Elsevier B.V. All rights reserved.

Low-cost PWM speed controller for an electric mini-baja type vehicle

This paperwork presents a Pulse Width Modulation (PWM) speed controller for an electric mini-baja-type car. A battery-fed 1-kW three-phase induction motor provides the electric vehicle traction. The open-loop speed control is implemented with an equal voltage/frequency ratio, in order to maintain a constant amount of torque on all velocities. The PWM is implemented by a low-cost 8-bit microcontroller provided with optimized ROM charts for distinct speed value implementations, synchronized transition between different charts and reduced odd harmonics generation. This technique was implemented using a single passenger mini-baja vehicle, and the essays have shown that its application resulted on reduced current consumption, besides eliminating mechanical parts. Copyright © 2007 by ABCM.

Technology assessment for power quality mitigation devices - Micro-DVR case study

This work presents a case study on technology assessment for power quality devices. A system compatibility test protocol for power quality mitigation devices was developed in order to evaluate the functionality of three-phase voltage restoration devices. In order to case test this test protocol, a development platform with reduced power for DVR (Dynamic Voltage Restorer), the Micro-DVR, was tested, and results were discussed based on voltage disturbances standards. ©2008 IEEE.

Efeito da implantação iônica por imersão em plasma no aço ferramenta tipo H13

Pós-graduação em Engenharia Mecânica - FEG

Caratterizzazione e generazione di segnali PWM per amplificatori in classe D ad alta efficienza

The convergence of information technology and consumer electronics towards battery powered portable devices has increased the interest in high efficiency, low dissipation amplifiers. Class D amplifiers are the state of the art in low power consumption and high performance amplification. In this thesis we explore the possibility of exploiting nonlinearities introduced by the PWM modulation, by designing an optimized modulation law which scales its carrier frequency adaptively with the input signal's average power while preserving the SNR, thus reducing power consumption. This is achieved by means of a novel analytical model of the PWM output spectrum, which shows how interfering harmonics and their bandwidth affect the spectrum. This allows for frequency scaling with negligible aliasing between the baseband spectrum and its harmonics. We performed low noise power spectrum measurements on PWM modulations generated by comparing variable bandwidth, random test signals with a variable frequency triangular wave carrier. The experimental results show that power-optimized frequency scaling is both feasible and effective. The new analytical model also suggests a new PWM architecture that can be applied to digitally encoded input signals which are predistorted and compared with a cosine carrier, which is accurately synthesized by a digital oscillator. This approach has been simulated in a realistic noisy model and tested in our measurement setup. A zero crossing search on the obtained PWM modulation law proves that this approach yields an equivalent signal quality with respect to traditional PWM schemes, while entailing the use of signals whose bandwidth is remarkably smaller due to the use of a cosine instead of a triangular carrier.