Rapid down-regulation of mammalian Period genes during behavioral resetting of the circadian clock

The pervasive role of circadian clocks in regulating physiology and behavior is widely recognized. Their adaptive value is their ability to be entrained by environmental cues such that the internal circadian phase is a reliable predictor of solar time. In mammals, both light and nonphotic behavioral cues can entrain the principal oscillator of the hypothalamic suprachiasmatic nuclei (SCN). However, although light can advance or delay the clock during circadian night, behavioral events trigger phase advances during the subjective day, when the clock is insensitive to light. The recent identification of Period (Per) genes in mammals, homologues of dperiod, which encodes a core element of the circadian clockwork in Drosophila, now provides the opportunity to explain circadian timing and entrainment at a molecular level. In mice, expression of mPer1 and mPer2 in the SCN is rhythmic and acutely up-regulated by light. Moreover, the temporal relations between mRNA and protein cycles are consistent with a clock based on a transcriptional/translational feedback loop. Here we describe circadian oscillations of Per1 and Per2 in the SCN of the Syrian hamster, showing that PER1 protein and mRNA cycles again behave in a manner consistent with a negative-feedback oscillator. Furthermore, we demonstrate that nonphotic resetting has the opposite effect to light: acutely down-regulating these genes. Their sensitivity to nonphotic resetting cues supports their proposed role as core elements of the circadian oscillator. Moreover, this study provides an explanation at the molecular level for the contrasting but convergent effects of photic and nonphotic cues on the clock.

Phosphorylation of the Neurospora clock protein FREQUENCY determines its degradation rate and strongly influences the period length of the circadian clock

Under free running conditions, FREQUENCY (FRQ) protein, a central component of the Neurospora circadian clock, is progressively phosphorylated, becoming highly phosphorylated before its degradation late in the circadian day. To understand the biological function of FRQ phosphorylation, kinase inhibitors were used to block FRQ phosphorylation in vivo and the effects on FRQ and the clock observed. 6-dimethylaminopurine (a general kinase inhibitor) is able to block FRQ phosphorylation in vivo, reducing the rate of phosphorylation and the degradation of FRQ and lengthening the period of the clock in a dose-dependent manner. To confirm the role of FRQ phosphorylation in this clock effect, phosphorylation sites in FRQ were identified by systematic mutagenesis of the FRQ ORF. The mutation of one phosphorylation site at Ser-513 leads to a dramatic reduction of the rate of FRQ degradation and a very long period (>30 hr) of the clock. Taken together, these data strongly suggest that FRQ phosphorylation triggers its degradation, and the degradation rate of FRQ is a major determining factor for the period length of the Neurospora circadian clock.

Vagaries of the molecular clock

The hypothesis of the molecular evolutionary clock asserts that informational macromolecules (i.e., proteins and nucleic acids) evolve at rates that are constant through time and for different lineages. The clock hypothesis has been extremely powerful for determining evolutionary events of the remote past for which the fossil and other evidence is lacking or insufficient. I review the evolution of two genes, Gpdh and Sod. In fruit flies, the encoded glycerol-3-phosphate dehydrogenase (GPDH) protein evolves at a rate of 1.1 × 10−10 amino acid replacements per site per year when Drosophila species are compared that diverged within the last 55 million years (My), but a much faster rate of ≈4.5 × 10−10 replacements per site per year when comparisons are made between mammals (≈70 My) or Dipteran families (≈100 My), animal phyla (≈650 My), or multicellular kingdoms (≈1100 My). The rate of superoxide dismutase (SOD) evolution is very fast between Drosophila species (16.2 × 10−10 replacements per site per year) and remains the same between mammals (17.2) or Dipteran families (15.9), but it becomes much slower between animal phyla (5.3) and still slower between the three kingdoms (3.3). If we assume a molecular clock and use the Drosophila rate for estimating the divergence of remote organisms, GPDH yields estimates of 2,500 My for the divergence between the animal phyla (occurred ≈650 My) and 3,990 My for the divergence of the kingdoms (occurred ≈1,100 My). At the other extreme, SOD yields divergence times of 211 My and 224 My for the animal phyla and the kingdoms, respectively. It remains unsettled how often proteins evolve in such erratic fashion as GPDH and SOD.

Interlocked feedback loops contribute to the robustness of the Neurospora circadian clock

Interlocked feedback loops may represent a common feature among the regulatory systems controlling circadian rhythms. The Neurospora circadian feedback loops involve white collar-1 (wc-1), wc-2, and frequency (frq) genes. We show that WC-1 and WC-2 proteins activate the transcription of frq gene, whereas FRQ protein plays dual roles: repressing its own transcription, probably by interacting with the WC-1/WC-2 complex, and activating the expression of both WC proteins. Thus, they form two interlocked feedback loops: one negative and one positive. We establish the physiological significance of the interlocked positive feedback loops by showing that the levels of WC-1 and WC-2 determine the robustness and stability of the clock. Our data demonstrate that with WC-1 being the limiting factor in the WC-1/WC-2 complex, the greater the levels of WC-1 and WC-2, the higher the level of the FRQ oscillation and the more robust the overt rhythms. Our data also show that, despite considerable changes in the levels of WC-1, WC-2, and FRQ, the period of the clock has been limited to a small range, suggesting that the interlocked circadian feedback loops are also important for determining the circadian period length of the clock.

The molecular basis of temperature compensation in the Arabidopsis circadian clock

Circadian clocks maintain robust and accurate timing over a broad range of physiological temperatures, a characteristic termed temperature compensation. In Arabidopsis thaliana, ambient temperature affects the rhythmic accumulation of transcripts encoding the clock components TIMING OF CAB EXPRESSION1 (TOC1), GIGANTEA (GI), and the partially redundant genes CIRCADIAN CLOCK ASSOCIATED1 (CCA1) and LATE ELONGATED HYPOCOTYL (LHY). The amplitude and peak levels increase for TOC1 and GI RNA rhythms as the temperature increases (from 17 to 27 degrees C), whereas they decrease for LHY. However, as temperatures decrease ( from 17 to 12 degrees C), CCA1 and LHY RNA rhythms increase in amplitude and peak expression level. At 27 degrees C, a dynamic balance between GI and LHY allows temperature compensation in wild-type plants, but circadian function is impaired in Ihy and gi mutant plants. However, at 12 degrees C, CCA1 has more effect on the buffering mechanism than LHY, as the cca1 and gi mutations impair circadian rhythms more than Ihy at the lower temperature. At 17 degrees C, GI is apparently dispensable for free-running circadian rhythms, although partial GI function can affect circadian period. Numerical simulations using the interlocking-loop model show that balancing LHY/CCA1 function against GI and other evening-expressed genes can largely account for temperature compensation in wild-type plants and the temperature-specific phenotypes of gi mutants.

The relationship between cognitive ability, insight and self-regulatory behaviors: Findings from the older driver population

Self-regulation is often promoted as a coping strategy that may allow older drivers to drive safely for longer. Self-regulation depends upon drivers making an accurate assessment of their own ability and having a willingness to practice self-regulatory behaviors to compensate for changes in ability. The current study explored the relationship between older drivers’ cognitive ability, their driving confidence and their use of self-regulation. An additional study aim was to explore the relationship between these factors and older drivers’ interest in driving programs. Seventy Australian drivers aged 65 years and over completed a questionnaire about their driving and a brief screening measure of cognitive ability (an untimed Clock Drawing Test). While all participants reported high levels of confidence regarding their driving ability, and agreed that they would continue driving in the foreseeable future, a notable proportion performed poorly on the Clock Drawing Test. Compared to older drivers who successfully completed the Clock Drawing Test, those who failed the cognitive test were significantly less likely to report driving self-regulation, and showed significantly less interest in being involved in driving programs. Older drivers with declining cognitive abilities may not be self-regulating their driving. This group also appears to be unlikely to self-refer to driving programs.

BabelFuse data fusion unit with precision wireless clock synchronisation

A significant issue encountered when fusing data received from multiple sensors is the accuracy of the timestamp associated with each piece of data. This is particularly important in applications such as Simultaneous Localisation and Mapping (SLAM) where vehicle velocity forms an important part of the mapping algorithms; on fastmoving vehicles, even millisecond inconsistencies in data timestamping can produce errors which need to be compensated for. The timestamping problem is compounded in a robot swarm environment due to the use of non-deterministic readily-available hardware (such as 802.11-based wireless) and inaccurate clock synchronisation protocols (such as Network Time Protocol (NTP)). As a result, the synchronisation of the clocks between robots can be out by tens-to-hundreds of milliseconds making correlation of data difficult and preventing the possibility of the units performing synchronised actions such as triggering cameras or intricate swarm manoeuvres. In this thesis, a complete data fusion unit is designed, implemented and tested. The unit, named BabelFuse, is able to accept sensor data from a number of low-speed communication buses (such as RS232, RS485 and CAN Bus) and also timestamp events that occur on General Purpose Input/Output (GPIO) pins referencing a submillisecondaccurate wirelessly-distributed "global" clock signal. In addition to its timestamping capabilities, it can also be used to trigger an attached camera at a predefined start time and frame rate. This functionality enables the creation of a wirelessly-synchronised distributed image acquisition system over a large geographic area; a real world application for this functionality is the creation of a platform to facilitate wirelessly-distributed 3D stereoscopic vision. A ‘best-practice’ design methodology is adopted within the project to ensure the final system operates according to its requirements. Initially, requirements are generated from which a high-level architecture is distilled. This architecture is then converted into a hardware specification and low-level design, which is then manufactured. The manufactured hardware is then verified to ensure it operates as designed and firmware and Linux Operating System (OS) drivers are written to provide the features and connectivity required of the system. Finally, integration testing is performed to ensure the unit functions as per its requirements. The BabelFuse System comprises of a single Grand Master unit which is responsible for maintaining the absolute value of the "global" clock. Slave nodes then determine their local clock o.set from that of the Grand Master via synchronisation events which occur multiple times per-second. The mechanism used for synchronising the clocks between the boards wirelessly makes use of specific hardware and a firmware protocol based on elements of the IEEE-1588 Precision Time Protocol (PTP). With the key requirement of the system being submillisecond-accurate clock synchronisation (as a basis for timestamping and camera triggering), automated testing is carried out to monitor the o.sets between each Slave and the Grand Master over time. A common strobe pulse is also sent to each unit for timestamping; the correlation between the timestamps of the di.erent units is used to validate the clock o.set results. Analysis of the automated test results show that the BabelFuse units are almost threemagnitudes more accurate than their requirement; clocks of the Slave and Grand Master units do not di.er by more than three microseconds over a running time of six hours and the mean clock o.set of Slaves to the Grand Master is less-than one microsecond. The common strobe pulse used to verify the clock o.set data yields a positive result with a maximum variation between units of less-than two microseconds and a mean value of less-than one microsecond. The camera triggering functionality is verified by connecting the trigger pulse output of each board to a four-channel digital oscilloscope and setting each unit to output a 100Hz periodic pulse with a common start time. The resulting waveform shows a maximum variation between the rising-edges of the pulses of approximately 39¥ìs, well below its target of 1ms.

Analysis of regionally enhanced GPS orbit and clock solutions and contribution to improvement of real-time precise point positioning

This work experimentally examines the performance benefits of a regional CORS network to the GPS orbit and clock solutions for supporting real-time Precise Point Positioning (PPP). The regionally enhanced GPS precise orbit solutions are derived from a global evenly distributed CORS network added with a densely distributed network in Australia and New Zealand. A series of computational schemes for different network configurations are adopted in the GAMIT-GLOBK and PANDA data processing. The precise GPS orbit results show that the regionally enhanced solutions achieve the overall orbit improvements with respect to the solutions derived from the global network only. Additionally, the orbital differences over GPS satellite arcs that are visible by any of the five Australia-wide CORS stations show a higher percentage of overall improvements compared to the satellite arcs that are not visible from these stations. The regional GPS clock and Uncalibrated Phase Delay (UPD) products are derived using the PANDA real time processing module from Australian CORS networks of 35 and 79 stations respectively. Analysis of PANDA kinematic PPP and kinematic PPP-AR solutions show certain overall improvements in the positioning performance from a denser network configuration after solution convergence. However, the clock and UPD enhancement on kinematic PPP solutions is marginal. It is suggested that other factors, such as effects of ionosphere, incorrectly fixed ambiguities, may be the more dominating, deserving further research attentions.

Precise relative clock synchronization for distributed control using TSC registers

Precise clock synchronization is essential in emerging time-critical distributed control systems operating over computer networks where the clock synchronization requirements are mostly focused on relative clock synchronization and high synchronization precision. Existing clock synchronization techniques such as the Network Time Protocol (NTP) and the IEEE 1588 standard can be difficult to apply to such systems because of the highly precise hardware clocks required, due to network congestion caused by a high frequency of synchronization message transmissions, and high overheads. In response, we present a Time Stamp Counter based precise Relative Clock Synchronization Protocol (TSC-RCSP) for distributed control applications operating over local-area networks (LANs). In our protocol a software clock based on the TSC register, counting CPU cycles, is adopted in the time clients and server. TSC-based clocks offer clients a precise, stable and low-cost clock synchronization solution. Experimental results show that clock precision in the order of 10~microseconds can be achieved in small-scale LAN systems. Such clock precision is much higher than that of a processor's Time-Of-Day clock, and is easily sufficient for most distributed real-time control applications over LANs.

Driving simulator evaluation of the failure of an audio in-vehicle warning for railway level crossings

It is impracticable to upgrade the 18,900 Australian passive crossings as such crossings are often located in remote areas, where power is lacking and with low road and rail traffic. The rail industry is interested in developing innovative in-vehicle technology interventions to warn motorists of approaching trains directly in their vehicles. The objective of this study was therefore to evaluate the benefits of the introduction of such technology. We evaluated the changes in driver performance once the technology is enabled and functioning correctly, as well as the effects of an unsafe failure of the technology? We conducted a driving simulator study where participants (N=15) were familiarised with an in-vehicle audio warning for an extended period. After being familiarised with the system, the technology started failing, and we tested the reaction of drivers with a train approaching. This study has shown that with the traditional passive crossings with RX2 signage, the majority of drivers complied (70%) and looked for trains on both sides of the rail track. With the introduction of the in-vehicle audio message, drivers did not approach crossings faster, did not reduce their safety margins and did not reduce their gaze towards the rail tracks. However participants’ compliance at the stop sign decreased by 16.5% with the technology installed in the vehicle. The effect of the failure of the in-vehicle audio warning technology showed that most participants did not experience difficulties in detecting the approaching train even though they did not receive any warning message. This showed that participants were still actively looking for trains with the system in their vehicle. However, two participants did not stop and one decided to beat the train when they did not receive the audio message, suggesting potential human factors issues to be considered with such technology.

Believe it or Not! Multicore CPUs can Match GPUs for FLOP-intensive Applications

In this work, we evaluate performance of a real-world image processing application that uses a cross-correlation algorithm to compare a given image with a reference one. The algorithm processes individual images represented as 2-dimensional matrices of single-precision floating-point values using O(n4) operations involving dot-products and additions. We implement this algorithm on a nVidia GTX 285 GPU using CUDA, and also parallelize it for the Intel Xeon (Nehalem) and IBM Power7 processors, using both manual and automatic techniques. Pthreads and OpenMP with SSE and VSX vector intrinsics are used for the manually parallelized version, while a state-of-the-art optimization framework based on the polyhedral model is used for automatic compiler parallelization and optimization. The performance of this algorithm on the nVidia GPU suffers from: (1) a smaller shared memory, (2) unaligned device memory access patterns, (3) expensive atomic operations, and (4) weaker single-thread performance. On commodity multi-core processors, the application dataset is small enough to fit in caches, and when parallelized using a combination of task and short-vector data parallelism (via SSE/VSX) or through fully automatic optimization from the compiler, the application matches or beats the performance of the GPU version. The primary reasons for better multi-core performance include larger and faster caches, higher clock frequency, higher on-chip memory bandwidth, and better compiler optimization and support for parallelization. The best performing versions on the Power7, Nehalem, and GTX 285 run in 1.02s, 1.82s, and 1.75s, respectively. These results conclusively demonstrate that, under certain conditions, it is possible for a FLOP-intensive structured application running on a multi-core processor to match or even beat the performance of an equivalent GPU version.

A weighted average-based external clock synchronisation protocol for wireless sensor networks

Wireless Sensor Networks (WSNs) have many application scenarios where external clock synchronisation may be required because a WSN may consist of components which are not connected to each other. In this paper, we first propose a novel weighted average-based internal clock synchronisation (WICS) protocol, which synchronises all the clocks of a WSN with the clock of a reference node periodically. Based on this protocol, we then propose our weighted average-based external clock synchronisation (WECS) protocol. We have analysed the proposed protocols for maximum synchronisation error and shown that it is always upper bounded. Extensive simulation studies of the proposed protocols have been carried out using Castalia simulator. Simulation results validate our above theoretical claim and also show that the proposed protocols perform better in comparison to other protocols in terms of synchronisation accuracy. A prototype implementation of the WICS protocol using a few TelosB motes also validates the above conclusions.

A weighted average based external clock synchronization protocol for wireless sensor networks

Clock synchronization is an extremely important requirement of wireless sensor networks(WSNs). There are many application scenarios such as weather monitoring and forecasting etc. where external clock synchronization may be required because WSN itself may consists of components which are not connected to each other. A usual approach for external clock synchronization in WSNs is to synchronize the clock of a reference node with an external source such as UTC, and the remaining nodes synchronize with the reference node using an internal clock synchronization protocol. In order to provide highly accurate time, both the offset and the drift rate of each clock with respect to reference node are estimated from time to time, and these are used for getting correct time from local clock reading. A problem with this approach is that it is difficult to estimate the offset of a clock with respect to the reference node when drift rate of clocks varies over a period of time. In this paper, we first propose a novel internal clock synchronization protocol based on weighted averaging technique, which synchronizes all the clocks of a WSN to a reference node periodically. We call this protocol weighted average based internal clock synchronization(WICS) protocol. Based on this protocol, we then propose our weighted average based external clock synchronization(WECS) protocol. We have analyzed the proposed protocols for maximum synchronization error and shown that it is always upper bounded. Extensive simulation studies of the proposed protocols have been carried out using Castalia simulator. Simulation results validate our theoretical claim that the maximum synchronization error is always upper bounded and also show that the proposed protocols perform better in comparison to other protocols in terms of synchronization accuracy. A prototype implementation of the proposed internal clock synchronization protocol using a few TelosB motes also validates our claim.

A Design for Performance Improvement of Clock Synchronization in WSNs using a TDMA-based MAC Protocol

Clock synchronization in a wireless sensor network (WSN) is quite essential as it provides a consistent and a coherent time frame for all the nodes across the network. Typically, clock synchronization is achieved by message passing using a contention-based scheme for media access, like carrier sense multiple access (CSMA). The nodes try to synchronize with each other, by sending synchronization request messages. If many nodes try to send messages simultaneously, contention-based schemes cannot efficiently avoid collisions. In such a situation, there are chances of collisions, and hence, message losses, which, in turn, affects the convergence of the synchronization algorithms. However, the number of collisions can be reduced with a frame based approach like time division multiple access (TDMA) for message passing. In this paper, we propose a design to utilize TDMA-based media access and control (MAC) protocol for the performance improvement of clock synchronization protocols. The basic idea is to use TDMA-based transmissions when the degree of synchronization improves among the sensor nodes during the execution of the clock synchronization algorithm. The design significantly reduces the collisions among the synchronization protocol messages. We have simulated the proposed protocol in Castalia network simulator. The simulation results show that the proposed protocol significantly reduces the time required for synchronization and also improves the accuracy of the synchronization algorithm.

A movable-cavity cold atom space clock

We present an experimental scheme of a cold atom space clock with a movable cavity. By using a single microwave cavity, we find that the clock has a significant advantage, i.e. the longitudinal cavity phase shift is eliminated. A theoretical analysis has been carried out in terms of the relation between the atomic transition probability and the velocity of the moving cavity by taking into account the velocity distribution of cold atoms. The requirements for the microwave power and its stability for atomic pi/2 excitation at different moving velocities of the cavity lead to the determination of the proper working parameters of the rubidium clock in frequency accuracy 10(-17). Finally, the mechanical stability for the scheme is analysed and the ways of solving the possible mechanical instability of the device are proposed.