Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Regenerating codes: A reformulated storage-bandwidth trade-off and a new construction

In this paper, the storage-repair-bandwidth (SRB) trade-off curve of regenerating codes is reformulated to yield a tradeoff between two global parameters of practical relevance, namely information rate and repair rate. The new information-repair-rate (IRR) tradeoff provides a different and insightful perspective on regenerating codes. For example, it provides a new motivation for seeking to investigate constructions corresponding to the interior of the SRB tradeoff. Interestingly, each point on the SRB tradeoff corresponds to a curve in the IRR tradeoff setup. We characterize completely, functional repair under the IRR framework, while for exact repair, an achievable region is presented. In the second part of this paper, a rate-half regenerating code for the minimum storage regenerating point is constructed that draws upon the theory of invariant subspaces. While the parameters of this rate-half code are the same as those of the MISER code, the construction itself is quite different.

Improving the Sensitivity and Bandwidth of In-Plane Capacitive Microaccelerometers Using Compliant Mechanical Amplifiers

This paper presents a method to enhance both the sensitivity and bandwidth of in-plane capacitive micromachined accelerometers by using compliant mechanical amplifiers, and thus obviating the compromise between the sensitivity and bandwidth. Here, we compare one of the most sensitive single-axis capacitive accelerometers and another with large resonant frequency reported in the literature with the modified designs that include displacement-amplifying compliant mechanisms (DaCMs) occupying the same footprint and under identical conditions. We show that 62% improvement in sensitivity and 34% improvement in bandwidth in the former, and 27% and 25% in the latter can be achieved. Also presented here is a dual-axis accelerometer that uses a suspension that decouples and amplifies the displacements along the two in-plane orthogonal axes. The new design was microfabricated, packaged, and tested. The device is 25-mu m thick with the interfinger gap as large as 4 m. Despite the simplicity of the microfabrication process, the measured axial sensitivity (static) of about 0.58 V/g for both the axes was achieved with a cross-axis sensitivity of less than +/- 2%. The measured natural frequency along the two in-plane axes was 920 Hz. Displacement amplification of 6.2 was obtained using the DaCMs in the dual-axis accelerometer. 2013-0083]

An Improved Outer Bound on the Storage-Repair-Bandwidth Tradeoff of Exact-Repair Regenerating Codes

While the tradeoff between the amount of data stored and the repair bandwidth of an (n, k, d) regenerating code has been characterized under functional repair (FR), the case of exact repair (ER) remains unresolved. It is known that there do not exist ER codes which lie on the FR tradeoff at most of the points. The question as to whether one can asymptotically approach the FR tradeoff was settled recently by Tian who showed that in the (4, 3, 3) case, the ER region is bounded away from the FR region. The FR tradeoff serves as a trivial outer bound on the ER tradeoff. In this paper, we extend Tian's results by establishing an improved outer bound on the ER tradeoff which shows that the ER region is bounded away from the FR region, for any (n; k; d). Our approach is analytical and builds upon the framework introduced earlier by Shah et. al. Interestingly, a recently-constructed, layered regenerating code is shown to achieve a point on this outer bound for the (5, 4, 4) case. This represents the first-known instance of an optimal ER code that does not correspond to a point on the FR tradeoff.

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth

In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultaneously achieves several objectives: (i) improved cache hit ratio, (ii) moving the tag storage overhead to DRAM, (iii) lower cache hit latency than tags-in-SRAM, and (iv) reduction in off-chip bandwidth wastage. The Bi-Modal Cache addresses the miss rate versus off-chip bandwidth dilemma by organizing the data in a bi-modal fashion - blocks with high spatial locality are organized as large blocks and those with little spatial locality as small blocks. By adaptively selecting the right granularity of storage for individual blocks at run-time, the proposed DRAM cache organization is able to make judicious use of the available DRAM cache capacity as well as reduce the off-chip memory bandwidth consumption. The Bi-Modal Cache improves cache hit latency despite moving the metadata to DRAM by means of a small SRAM based Way Locator. Further by leveraging the tremendous internal bandwidth and capacity that stacked DRAM organizations provide, the Bi-Modal Cache enables efficient concurrent accesses to tags and data to reduce hit time. Through detailed simulations, we demonstrate that the Bi-Modal Cache achieves overall performance improvement (in terms of Average Normalized Turnaround Time (ANTT)) of 10.8%, 13.8% and 14.0% in 4-core, 8-core and 16-core workloads respectively.

Gain bandwidth characterization of surface-emitting quantum well laser gain structures for femtosecond operation

We present a method to experimentally characterize the gain filter and calculate a corresponding parabolic gain bandwidth of lasers that are described by "class A" dynamics by solving the master equation of spectral condensation for Gaussian spectra. We experimentally determine the gain filter, with an equivalent parabolic gain bandwidth of up to 51 nm, for broad-band InGaAs/GaAs quantum well gain surface-emitting semiconductor laser structures capable of producing pulses down to 60 fs width when mode-locked with an optical Stark saturable absorber mirror. © 2010 Optical Society of America.

Efficient line launch for bandwidth improvement of 10 Gbit/s multimode fibre links using elliptical Gaussian beam

A novel elliptical Gaussian beam line launch is shown to allow improved system capacity for high speed multimode fibre links. This launch maintains higher bandwidth than dual launch even with misalignment of ±6 μm despite not requiring testing at installation. ©2010 IEEE.