System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real-time or near-real-time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field-programmable gate arrays (FPGAs), are widely used. This paper proposes an FPGA-based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low-cost Xilinx Zynq board with a Zynq-7020 system-on-chip FPGA-based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low-cost embedded systems, opening perspectives for onboard hyperspectral image processing.

Stress-triggered synaptic malfunction: a gate along the path from depressionto dementia

Tese de Doutoramento em Ciências da Saúde.

T-type Ca2+ channels, SK2 channels and SERCAs gate sleep-related oscillations in thalamic dendrites.

T-type Ca2+ channels (T channels) underlie rhythmic burst discharges during neuronal oscillations that are typical during sleep. However, the Ca2+-dependent effectors that are selectively regulated by T currents remain unknown. We found that, in dendrites of nucleus reticularis thalami (nRt), intracellular Ca2+ concentration increases were dominated by Ca2+ influx through T channels and shaped rhythmic bursting via competition between Ca2+-dependent small-conductance (SK)-type K+ channels and Ca2+ uptake pumps. Oscillatory bursting was initiated via selective activation of dendritically located SK2 channels, whereas Ca2+ sequestration by sarco/endoplasmic reticulum Ca2+-ATPases (SERCAs) and cumulative T channel inactivation dampened oscillations. Sk2-/- (also known as Kcnn2) mice lacked cellular oscillations, showed a greater than threefold reduction in low-frequency rhythms in the electroencephalogram of non-rapid-eye-movement sleep and had disrupted sleep. Thus, the interplay of T channels, SK2 channels and SERCAs in nRt dendrites comprises a specialized Ca2+ signaling triad to regulate oscillatory dynamics related to sleep.

Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Lexan Gate Arm, HR-536, 1987

Innovative Rail Ltd. of Cedar Rapids, Iowa produced a new rail/highway crossing gate arm that shows promise in two areas: a. Minimizing arm breakage, and b. Added target value to motorists. The new gate was demonstrated to the Chicago and North Western Transportation Company, and that railroad has requested its use at two crossings on an "experimental basis" to determine if its installation provides relief in those areas. On April 18, 1986, the Department observed a test of the material under field conditions with the Transportation Company. The gate received four mid-center strikes at 5 MPH by a company truck while in the lowered position, and showed no damage. In a fifth mid-center strike at 15 MPH, the gate was visibly damaged at the connection to its raising mechanism, but continued to function though at a 5-10 degree drop. Several pictures of the gate and its saddle mechanism are shown in Appendix A of this report. Innovative Rail established distributorships in the United States and Canada, and has since gone out of business.

A wearable system to time gate crossing during alpine skiing slalom

INTRODUCTION: In alpine skiing, chronometry analysis is currently the most common tool to assess performance. It is widely used to rank competitors during races, as well as to manage athletes training and to evaluate material. Usually, this measurement is accurately realized using timing cells. Nevertheless, these devices are too complex and expensive to allow chronometry of every gates crossing. On the other side, differential GPS can be used for measuring gate crossing time (Waegli et al). However, this is complex (e.g. recording gate position with GPS) and mainly used in research applications. The aim of the study was to propose a wearable system to time gates crossing during alpine skiing slalom (SL), which is suitable for routine uses. METHODS: The proposed system was composed of a 3D accelerometer (ADXL320®, Analog Device, USA) placed at the sacrum of the athlete, a matrix of force sensors (Flexiforce®, Tekscan, USA) fixed on the right shin guard and a data logger (Physilog®, BioAGM, Switzerland). The sensors were sampled at 500 Hz. The crossing time were calculated in two phases. First, the accelerometer was used to detect the curves by considering the maximum of the mediolateral peak acceleration. Then, the force sensors were used to detect the impacts with the gates by considering maximum force variation. In case of non impact, the detection was realized based on the acceleration and features measured at the other gates. In order to assess the efficiency of the system, two different SL were monitored twice for two world cup level skiers, a male SL expert and a female downhill expert. RESULTS AND DISCUSSION: The combination of the accelerometer and force sensors allowed to clearly identify the gate crossing times. When comparing the runs of the SL expert and the downhill expert, we noticed that the SL expert was faster. For example for the first SL, the overall difference between the best run of each athlete was of 5.47s. At each gate, the SL expert increased the time difference slower at the beginning (0.27s/gate) than at the end (0.34s/gate). Furthermore, when comparing the runs of the SL expert, a maximum time difference of 20ms at each gate was noticed. This showed high repeatability skills of the SL expert. In opposite, the downhill expert with a maximum difference time of 1s at each gate was clearly less repeatable. Both skiers were not disturbed by the system. CONCLUSION: This study proposed a new wearable system to automatically time gates crossing during alpine skiing slalom combining force and accelerometer sensors. The system was evaluated with two professional world cup skiers and showed a high potential. This system could be extended to time other parameters. REFERENCES Waegli A, Skaloud J (2007). Inside GNSS, Spring, 24-34.

Top-gate microcrystalline silicon TFTs processed at low temperature (<200ºC)

N-type as well P-type top-gate microcrystalline silicon thin film transistors (TFTs) are fabricated on glass substrates at a maximum temperature of 200 °C. The active layer is an undoped μc-Si film, 200 nm thick, deposited by Hot-Wire Chemical Vapor. The drain and source regions are highly phosphorus (N-type TFTs) or boron (P-type TFTs)-doped μc-films deposited by HW-CVD. The gate insulator is a silicon dioxide film deposited by RF sputtering. Al-SiO 2-N type c-Si structures using this insulator present low flat-band voltage,-0.2 V, and low density of states at the interface D it=6.4×10 10 eV -1 cm -2. High field effect mobility, 25 cm 2/V s for electrons and 1.1 cm 2/V s for holes, is obtained. These values are very high, particularly the hole mobility that was never reached previously.

Efficiency and reliability enhancement of silicon nanocrystal field-effect luminescence from nitride-oxide gate stacks

We report on a field-effect light emitting device based on silicon nanocrystals in silicon oxide deposited by plasma-enhanced chemical vapor deposition. The device shows high power efficiency and long lifetime. The power efficiency is enhanced up to 0.1 %25 by the presence of a silicon nitride control layer. The leakage current reduction induced by this nitride buffer effectively increases the power efficiency two orders of magnitude with regard to similarly processed devices with solely oxide. In addition, the nitride cools down the electrons that reach the polycrystalline silicon gate lowering the formation of defects, which significantly reduces the device degradation.

Role of PheE15 gate in ligand entry and nitric oxide detoxification function of Mycobacterium tuberculosis truncated hemoglobin N

The truncated hemoglobin N, HbN, of Mycobacterium tuberculosis is endowed with a potent nitric oxide dioxygenase (NOD) activity that allows it to relieve nitrosative stress and enhance in vivo survival of its host. Despite its small size, the protein matrix of HbN hosts a two-branched tunnel, consisting of orthogonal short and long channels, that connects the heme active site to the protein surface. A novel dual-path mechanism has been suggested to drive migration of O(2) and NO to the distal heme cavity. While oxygen migrates mainly by the short path, a ligand-induced conformational change regulates opening of the long tunnel branch for NO, via a phenylalanine (PheE15) residue that acts as a gate. Site-directed mutagenesis and molecular simulations have been used to examine the gating role played by PheE15 in modulating the NOD function of HbN. Mutants carrying replacement of PheE15 with alanine, isoleucine, tyrosine and tryptophan have similar O(2)/CO association kinetics, but display significant reduction in their NOD function. Molecular simulations substantiated that mutation at the PheE15 gate confers significant changes in the long tunnel, and therefore may affect the migration of ligands. These results support the pivotal role of PheE15 gate in modulating the diffusion of NO via the long tunnel branch in the oxygenated protein, and hence the NOD function of HbN.

Field-Programmable Gate Array Card for Readout and Control of Cryoelectronics

The main goal of the present Master’s Thesis project was to create a field-programmable gate array (FPGA) based system for the control of single-electron transistors or other cryoelectronic devices. The FPGA and similar technologies are studied in the present work. The fixed and programmable logic are compared with each other. The main features and limitations of the hardware used in the project are investigated. The hardware and software connections of the device to the computer are shown in detail. The software development techniques for FPGA-based design are described. The steps of design for programmable logic are considered. Furthermore, the results of filters implemented in the software are illustrated.