The construction and negotiation of identity and face in post observation feedback

Identity influences the practice of English language teachers and supervisors, their professional development and their ability to incorporate innovation and change. Talk during post observation feedback meetings provides participants with opportunities to articulate, construct, verify, contest and negotiate identities, processes which often engender issues of face. This study examines the construction and negotiation of identity and face in post observation feedback meetings between in-service English language teachers and supervisors at a tertiary institution in the United Arab Emirates. Within a linguistic ethnography framework, this study combined linguistic microanalysis of audio recorded feedback meetings with ethnographic data gathered from participant researcher knowledge, pre-analysis interviews and post-analysis participant interpretation interviews. Through a detailed, empirical description of situated ‘real life’ institutional talk, this study shows that supervisors construct identities involving authority, power, expertise, knowledge and experience while teachers index identities involving experience, knowledge and reflection. As well as these positive valued identities, other negative, disvalued identities are constructed. Identities are shown to be discursively claimed, verified, contested and negotiated through linguistic actions. This study also shows a link between identity and face. Analysis demonstrates that identity claims verified by an interactional partner can lead to face maintenance or support. However, a contested identity claim can lead to face threat which is usually managed by facework. Face, like identity, is found to be interactionally achieved and endogenous to situated discourse. Teachers and supervisors frequently risk face threat to protect their own identities, to contest their interactional partner’s identities or to achieve the feedback meeting goal i.e. improved teaching. Both identity and face are found to be consequential to feedback talk and therefore influence teacher development, teacher/supervisor relationships and the acceptance of feedback. Analysis highlights the evaluative and conforming nature of feedback in this context which may be hindering opportunities for teacher development.

Codificador JPEG baseado em FPGA

O presente trabalho consiste na implementação em hardware de unidades funcionais dedicadas e optimizadas, para a realização das operações de codificação e descodificação, definidas na norma de codificação com perda Joint Photographic Experts Group (JPEG), ITU-T T.81 ISO/IEC 10918-1. Realiza-se um estudo sobre esta norma de forma a caracterizar os seus principais blocos funcionais. A finalidade deste estudo foca-se na pesquisa e na proposta de optimizações, de forma a minimizar o hardware necessário para a realização de cada bloco, de modo a que o sistema realizado obtenha taxas de compressão elevadas, minimizando a distorção obtida. A redução de hardware de cada sistema, codificador e descodificador, é conseguida à custa da manipulação das equações dos blocos Forward Discrete Cosine Transform (FDCT) e Quantificação (Q) e dos blocos Forward Discrete Cosine Transform (IDCT) e Quantificação Inversa (IQ). Com as conclusões retiradas do estudo e através da análise de estruturas conhecidas, descreveu-se cada bloco em Very-High-Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) e fez-se a sua síntese em Field Programmable Gate Array (FPGA). Cada sistema implementado recorre à execução de cada bloco em paralelo de forma a optimizar a codificação/descodificação. Assim, para o sistema codificador, será realizada a operação da FDCT e Quantificação sobre duas matrizes diferentes e em simultâneo. O mesmo sucede para o sistema descodificador, composto pelos blocos Quantificação Inversa e IDCT. A validação de cada bloco sintetizado é executada com recurso a vectores de teste obtidos através do estudo efectuado. Após a integração de cada bloco, verificou-se que, para imagens greyscale de referência com resolução de 256 linhas por 256 colunas, é necessário 820,5 μs para a codificação de uma imagem e 830,5 μs para a descodificação da mesma. Considerando uma frequência de trabalho de 100 MHz, processam-se aproximadamente 1200 imagens por segundo.

Sistema de reconhecimento de impressões digitais baseado em FPGA

Trabalho de Projeto para obtenção do grau de Mestre em Engenharia de Eletrónica e Telecomunicações

Reconfigurable IEEE1451-FPGA based weblab infrastructure

Weblabs are spreading their influence in Science and Engineering (S&E) courses providing a way to remotely conduct real experiments. Typically, they are implemented by different architectures and infrastructures supported by Instruments and Modules (I&Ms) able to be remotely controlled and observed. Besides the inexistence of a standard solution for implementing weblabs, their reconfiguration is limited to a setup procedure that enables interconnecting a set of preselected I&Ms into an Experiment Under Test (EUT). Moreover, those I&Ms are not able to be replicated or shared by different weblab infrastructures, since they are usually based on hardware platforms. Thus, to overcome these limitations, this paper proposes a standard solution that uses I&Ms embedded into Field-Programmable Gate Array (FPGAs) devices. It is presented an architecture based on the IEEE1451.0 Std. supported by a FPGA-based weblab infrastructure able to be remotely reconfigured with I&Ms, described through standard Hardware Description Language (HDL) files, using a Reconfiguration Tool (RecTool).

Embedding instruments & modules into an IEEE1451-FPGA-Based Weblab infrastructure

Adopting standard-based weblab infrastructures can be an added value for spreading their influence and acceptance in education. This paper suggests a solution based on the IEEE1451.0 Std. and FPGA technology for creating reconfigurable weblab infrastructures using Instruments and Modules (I&Ms) described through standard Hardware Description Language (HDL) files. It describes a methodology for creating and binding I&Ms into an IEEE1451-module embedded in a FPGA-based board able to be remotely controlled/accessed using IEEE1451-HTTP commands. At the end, an example of a step-motor controller module bond to that IEEE1451-module is described.

Projeto e implementação de um pré-regulador de fator de potência com controlo digital

Hoje em dia as fontes de alimentação possuem correção do fator de potência, devido às diversas normas regulamentares existentes, que introduziram grandes restrições no que respeita à distorção harmónica (THD) e fator de potência (FP). Este trabalho trata da análise, desenvolvimento e implementação de um Pré-Regulador de fator de potência com controlo digital. O controlo digital de conversores com recurso a processamento digital de sinal tem vindo a ser ao longo dos últimos anos, objeto de investigação e desenvolvimento, estando constantemente a surgirem modificações nas topologias existentes. Esta dissertação tem como objetivo estudar e implementar um Pré-Regulador Retificador Boost e o respetivo controlo digital. O controlo do conversor é feito através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado num dispositivo FPGA (Field Programmable Gate Array) Spartan-3E. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos controladores. Para efetuar este controlo é necessário adquirir os sinais da corrente de entrada, tensão de entrada e tensão de saída. O sinal resultante do módulo de controlo é um sinal de PWM com valor de fator de ciclo variável ao longo do tempo. O projeto é simulado e validado através da plataforma MatLab/Simulink e PSIM, onde são apresentados resultados para o regime permanente e para transitórios da carga e da tensão de alimentação. Finalmente, o Pré-Regulador Retificador Boost controlado de forma digital é implementado em laboratório. Os resultados experimentais são apresentados para validar a metodologia e o projeto desenvolvidos.

Projecto e implementação de osciloscópio digital baseado na norma IEEE1451.0

Os osciloscópios digitais são utilizados em diversas áreas do conhecimento, assumindo-se no âmbito da engenharia electrónica, como instrumentos indispensáveis. Graças ao advento das Field Programmable Gate Arrays (FPGAs), os instrumentos de medição reconfiguráveis, dadas as suas vantagens, i.e., altos desempenhos, baixos custos e elevada flexibilidade, são cada vez mais uma alternativa aos instrumentos tradicionalmente usados nos laboratórios. Tendo como objectivo a normalização no acesso e no controlo deste tipo de instrumentos, esta tese descreve o projecto e implementação de um osciloscópio digital reconfigurável baseado na norma IEEE 1451.0. Definido de acordo com uma arquitectura baseada nesta norma, as características do osciloscópio são descritas numa estrutura de dados denominada Transducer Electronic Data Sheet (TEDS), e o seu controlo é efectuado utilizando um conjunto de comandos normalizados. O osciloscópio implementa um conjunto de características e funcionalidades básicas, todas verificadas experimentalmente. Destas, destaca-se uma largura de banda de 575kHz, um intervalo de medição de 0.4V a 2.9V, a possibilidade de se definir um conjunto de escalas horizontais, o nível e declive de sincronismo e o modo de acoplamento com o circuito sob análise. Arquitecturalmente, o osciloscópio é constituído por um módulo especificado com a linguagem de descrição de hardware (HDL, Hardware Description Language) Verilog e por uma interface desenvolvida na linguagem de programação Java®. O módulo é embutido numa FPGA, definindo todo o processamento do osciloscópio. A interface permite o seu controlo e a representação do sinal medido. Durante o projecto foi utilizado um conversor Analógico/Digital (A/D) com uma frequência máxima de amostragem de 1.5MHz e 14 bits de resolução que, devido às suas limitações, obrigaram à implementação de um sistema de interpolação multi-estágio com filtros digitais.

Comparative leaf morphological analysis of 20 species of Chrysobalanaceae

Morphological studies focusing on vegetative traits are useful in identifying species when fertile material is not available. The aim of this study was to assess the application of comparative leaf morphology to identify species of the Chrysobalanaceae family. The morphological observations were made with a stereomicroscope. We used the diaphanization technique for viewing venation details. It is shown the descriptions of the leaf morphology, illustrations and an identification key for 20 species from genera Couepia, Licania and Parinari (Chrysobalanaceae) occurring in the Adolpho Ducke Forest Reserve, Manaus, AM, Brazil. The key was constructed using the DELTA (DEscription Language for TAxonomy) software. Leaf traits such as the presence of intersecondary venation and the type of insertion of secondary veins were recorded for each species. These morphological leaf traits are reliable for identifying species of Chrysobalanaceae

On the verification of architectural reconfigurations

In a reconfigurable system, the response to contextual or internal change may trigger reconfiguration events which, on their turn, activate scripts that change the system׳s architecture at runtime. To be safe, however, such reconfigurations are expected to obey the fundamental principles originally specified by its architect. This paper introduces an approach to ensure that such principles are observed along reconfigurations by verifying them against concrete specifications in a suitable logic. Architectures, reconfiguration scripts, and principles are specified in Archery, an architectural description language with formal semantics. Principles are encoded as constraints, which become formulas of a two-layer graded hybrid logic, where the upper layer restricts reconfigurations, and the lower layer constrains the resulting configurations. Constraints are verified by translating them into logic formulas, which are interpreted over models derived from Archery specifications of architectures and reconfigurations. Suitable notions of bisimulation and refinement, to which the architect may resort to compare configurations, are given, and their relationship with modal validity is discussed.

Sistema gràfic de depuració per xarxes (NoC)

Aquest projecte descriu el disseny i desenvolupament d’una eina gràfica per a la depuració de projectes desenvolupats amb un llenguatge de descripció de sistemes com és el SystemC. Amb aquest llenguatge s’ha desenvolupat una NoC (Network on Chip). L’eina desenvolupada mostra de forma visual l’arquitectura de la xarxa NoC, els valors dels senyals que es transmeten a través de la xarxa i estadístiques sobre aquests per tal de poder fer un seguiment exhaustiu i agilitzar la recerca d’errors com interbloquejos, pèrdua de dades i d’altres. Al concentrar en un únic entorn la descripció de la NoC i les dades relatives a les senyals en temps de simulació, proporciona un valor afegit a altres eines disponibles per a realitzar aquesta tasca.

La biblioteca recombinada: portals i persones

Aquest article explora el disseny i l'ús dels portals en un entorn bibliotecari. Tracta les motivacions per construir portals, així com l'estructura i la tipologia d'aquests. A més, examina l'entorn de l'usuari en què es desenvolupen aquests portals. També argumenta que aporten serveis útils d'integració i presentació, però que s'han de considerar com a component d'un conjunt de serveis més ampli que la biblioteca està construint per tal d'introduir aquests recursos útils als usuaris. Així mateix, considera breument els serveis que els portals ofereixen: consulta distribuïda o metacerca, personalització, demandes, resolució OpenURL, avisos, etc. També considera l'emergent necessitat de serveis de directori o de registre per a coses com la descripció de col·leccions i serveis, dades de drets i polítiques, etc. Tracta l'impacte dels serveis web i el canvi en els models d'investigació i aprenentatge en relació al subministrament i ús d'informació en xarxa. Finalment, considera els serveis bibliotecaris com a part d'un entorn de sistemes, cada vegada més ric, que inclou els sistemes de gestió d'aprenentatge i de programari educatiu, portals de campus, serveis compartits com l'autenticació, i altres sistemes i serveis.

Estudi del model de representació XML/RDF

L'objectiu fonamental d'aquest treball és estudiar les relacions que hi ha a nivell teòric entre XML (eXtensible Markup Language) i RDF (Resource Description Language).

Browsing a component library using Non-functional Information

This paper highlights the role of non-functional information when reusing from a component library. We describe a method for selecting appropriate implementations of Ada packages taking non-functional constraints into account; these constraints model the context of reuse. Constraints take the form of queries using an interface description language called NoFun, which is also used to state non-functional information in Ada packages; query results are trees of implementations, following the import relationships between components. We define two different situations when reusing components, depending whether we take the library being searched as closed or extendible. The resulting tree of implementations can be manipulated by the user to solve ambiguities, to state default behaviours, and by the like. As part of the proposal, we face the problem of computing from code the non-functional information that determines the selection process.

The business model ontology a proposition in a design science approach

The goal of this dissertation is to find and provide the basis for a managerial tool that allows a firm to easily express its business logic. The methodological basis for this work is design science, where the researcher builds an artifact to solve a specific problem. In this case the aim is to provide an ontology that makes it possible to explicit a firm's business model. In other words, the proposed artifact helps a firm to formally describe its value proposition, its customers, the relationship with them, the necessary intra- and inter-firm infrastructure and its profit model. Such an ontology is relevant because until now there is no model that expresses a company's global business logic from a pure business point of view. Previous models essentially take an organizational or process perspective or cover only parts of a firm's business logic. The four main pillars of the ontology, which are inspired by management science and enterprise- and processmodeling, are product, customer interface, infrastructure and finance. The ontology is validated by case studies, a panel of experts and managers. The dissertation also provides a software prototype to capture a company's business model in an information system. The last part of the thesis consists of a demonstration of the value of the ontology in business strategy and Information Systems (IS) alignment. Structure of this thesis: The dissertation is structured in nine parts: Chapter 1 presents the motivations of this research, the research methodology with which the goals shall be achieved and why this dissertation present a contribution to research. Chapter 2 investigates the origins, the term and the concept of business models. It defines what is meant by business models in this dissertation and how they are situated in the context of the firm. In addition this chapter outlines the possible uses of the business model concept. Chapter 3 gives an overview of the research done in the field of business models and enterprise ontologies. Chapter 4 introduces the major contribution of this dissertation: the business model ontology. In this part of the thesis the elements, attributes and relationships of the ontology are explained and described in detail. Chapter 5 presents a case study of the Montreux Jazz Festival which's business model was captured by applying the structure and concepts of the ontology. In fact, it gives an impression of how a business model description based on the ontology looks like. Chapter 6 shows an instantiation of the ontology into a prototype tool: the Business Model Modelling Language BM2L. This is an XML-based description language that allows to capture and describe the business model of a firm and has a large potential for further applications. Chapter 7 is about the evaluation of the business model ontology. The evaluation builds on literature review, a set of interviews with practitioners and case studies. Chapter 8 gives an outlook on possible future research and applications of the business model ontology. The main areas of interest are alignment of business and information technology IT/information systems IS and business model comparison. Finally, chapter 9 presents some conclusions.

FPGA-Based Control Design for Power Electronic Applications

Tehoelektoniikkalaitteella tarkoitetaan ohjaus- ja säätöjärjestelmää, jolla sähköä muokataan saatavilla olevasta muodosta haluttuun uuteen muotoon ja samalla hallitaan sähköisen tehon virtausta lähteestä käyttökohteeseen. Tämä siis eroaa signaalielektroniikasta, jossa sähköllä tyypillisesti siirretään tietoa hyödyntäen eri tiloja. Tehoelektroniikkalaitteita vertailtaessa katsotaan yleensä niiden luotettavuutta, kokoa, tehokkuutta, säätötarkkuutta ja tietysti hintaa. Tyypillisiä tehoelektroniikkalaitteita ovat taajuudenmuuttajat, UPS (Uninterruptible Power Supply) -laitteet, hitsauskoneet, induktiokuumentimet sekä erilaiset teholähteet. Perinteisesti näiden laitteiden ohjaus toteutetaan käyttäen mikroprosessoreja, ASIC- (Application Specific Integrated Circuit) tai IC (Intergrated Circuit) -piirejä sekä analogisia säätimiä. Tässä tutkimuksessa on analysoitu FPGA (Field Programmable Gate Array) -piirien soveltuvuutta tehoelektroniikan ohjaukseen. FPGA-piirien rakenne muodostuu erilaisista loogisista elementeistä ja niiden välisistä yhdysjohdoista.Loogiset elementit ovat porttipiirejä ja kiikkuja. Yhdysjohdot ja loogiset elementit ovat piirissä kiinteitä eikä koostumusta tai lukumäärää voi jälkikäteen muuttaa. Ohjelmoitavuus syntyy elementtien välisistä liitännöistä. Piirissä on lukuisia, jopa miljoonia kytkimiä, joiden asento voidaan asettaa. Siten piirin peruselementeistä voidaan muodostaa lukematon määrä erilaisia toiminnallisia kokonaisuuksia. FPGA-piirejä on pitkään käytetty kommunikointialan tuotteissa ja siksi niiden kehitys on viime vuosina ollut nopeaa. Samalla hinnat ovat pudonneet. Tästä johtuen FPGA-piiristä on tullut kiinnostava vaihtoehto myös tehoelektroniikkalaitteiden ohjaukseen. Väitöstyössä FPGA-piirien käytön soveltuvuutta on tutkittu käyttäen kahta vaativaa ja erilaista käytännön tehoelektroniikkalaitetta: taajuudenmuuttajaa ja hitsauskonetta. Molempiin testikohteisiin rakennettiin alan suomalaisten teollisuusyritysten kanssa soveltuvat prototyypit,joiden ohjauselektroniikka muutettiin FPGA-pohjaiseksi. Lisäksi kehitettiin tätä uutta tekniikkaa hyödyntävät uudentyyppiset ohjausmenetelmät. Prototyyppien toimivuutta verrattiin vastaaviin perinteisillä menetelmillä ohjattuihin kaupallisiin tuotteisiin ja havaittiin FPGA-piirien mahdollistaman rinnakkaisen laskennantuomat edut molempien tehoelektroniikkalaitteiden toimivuudessa. Työssä on myösesitetty uusia menetelmiä ja työkaluja FPGA-pohjaisen säätöjärjestelmän kehitykseen ja testaukseen. Esitetyillä menetelmillä tuotteiden kehitys saadaan mahdollisimman nopeaksi ja tehokkaaksi. Lisäksi työssä on kehitetty FPGA:n sisäinen ohjaus- ja kommunikointiväylärakenne, joka palvelee tehoelektroniikkalaitteiden ohjaussovelluksia. Uusi kommunikointirakenne edistää lisäksi jo tehtyjen osajärjestelmien uudelleen käytettävyyttä tulevissa sovelluksissa ja tuotesukupolvissa.