Dynamic compact thermal models with multiple power sources: application to an ultrathin chip stacking technology

Whereas numerical modeling using finite-element methods (FEM) can provide transient temperature distribution in the component with enough accuracy, it is of the most importance the development of compact dynamic thermal models that can be used for electrothermal simulation. While in most cases single power sources are considered, here we focus on the simultaneous presence of multiple sources. The thermal model will be in the form of a thermal impedance matrix containing the thermal impedance transfer functions between two arbitrary ports. Eachindividual transfer function element ( ) is obtained from the analysis of the thermal temperature transient at node ¿ ¿ after a power step at node ¿ .¿ Different options for multiexponential transient analysis are detailed and compared. Among the options explored, small thermal models can be obtained by constrained nonlinear least squares (NLSQ) methods if the order is selected properly using validation signals. The methods are applied to the extraction of dynamic compact thermal models for a new ultrathin chip stack technology (UTCS).

State-of-the-art of 3D cultures (organs-on-a-chip) in safety testing and pathophysiology.

Integrated approaches using different in vitro methods in combination with bioinformatics can (i) increase the success rate and speed of drug development; (ii) improve the accuracy of toxicological risk assessment; and (iii) increase our understanding of disease. Three-dimensional (3D) cell culture models are important building blocks of this strategy which has emerged during the last years. The majority of these models are organotypic, i.e., they aim to reproduce major functions of an organ or organ system. This implies in many cases that more than one cell type forms the 3D structure, and often matrix elements play an important role. This review summarizes the state of the art concerning commonalities of the different models. For instance, the theory of mass transport/metabolite exchange in 3D systems and the special analytical requirements for test endpoints in organotypic cultures are discussed in detail. In the next part, 3D model systems for selected organs--liver, lung, skin, brain--are presented and characterized in dedicated chapters. Also, 3D approaches to the modeling of tumors are presented and discussed. All chapters give a historical background, illustrate the large variety of approaches, and highlight up- and downsides as well as specific requirements. Moreover, they refer to the application in disease modeling, drug discovery and safety assessment. Finally, consensus recommendations indicate a roadmap for the successful implementation of 3D models in routine screening. It is expected that the use of such models will accelerate progress by reducing error rates and wrong predictions from compound testing.

Crack Development in Ternary Mix Concrete Utilizing Various Saw Depths, TR-587, 2009

Early entry sawing applies sawing earlier and more shallowly than conventional sawing and is believed to increase sawing productivity and reduce the cost of the joint sawing operations. However, some early entry sawing joints (transverse joints) in Iowa were found to experience delayed cracking, sometimes up to 30 days. A concern is whether early entry sawing can lead to late-age random cracking. The present study investigated the effects of different sawing methods on random cracking in portland cement concrete (PCC) pavements. The approach was to assess the cracking potential at sawing joints by measuring the strain development of the concrete at the joints using concrete embedment strain gages. Ten joints were made with the early entry sawing method to a depth of 1.5 in., and two strain gages were installed in each of the joints. Another ten joints were made with the conventional sawing method, five of which were sawed to a depth of one-third of the pavement thickness (3.3 in.), and the other five of which were sawed to a depth of one-quarter of the pavement thickness (2.5 in.). One strain gage was installed in each joint made using conventional sawing. In total, 30 strain gages were installed in 20 joints. The results from the present study indicate that all 30 joints cracked within 25 days after paving, though most joints made using early entry sawing cracked later than the joints made using conventional sawing. No random cracking was observed in the early entry sawing test sections two months after construction. Additionally, it was found that the strain gages used were capable of monitoring the deformations at the joints. The joint crack times (or crack initiation time) measured by the strain gages were generally consistent with the visual observations.

Comparison of Setting Time Measured Using Ultrasonic Wave Propagation with Saw-Cutting Times on Pavements, TR-675, 2015

At present, there is little fundamental guidance available to assist contractors in choosing when to schedule saw cuts on joints. To conduct pavement finishing and sawing activities effectively, however, contractors need to know when a concrete mixture is going to reach initial set, or when the sawing window will open. Previous research investigated the use of the ultrasonic pulse velocity (UPV) method to predict the saw-cutting window for early entry sawing. The results indicated that the method has the potential to provide effective guidance to contractors as to when to conduct early entry sawing. The aim of this project was to conduct similar work to observe the correlation between initial setting and conventional sawing time. Sixteen construction sites were visited in Minnesota and Missouri over a two-year period. At each site, initial set was determined using a p-wave propagation technique with a commercial device. Calorimetric data were collected using a commercial semi-adiabatic device at a majority of the sites. Concrete samples were collected in front of the paver and tested using both methods with equipment that was set up next to the pavement during paving. The data collected revealed that the UPV method looks promising for early entry and conventional sawing in the field, both early entry and conventional sawing times can be predicted for the range of mixtures tested.

On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits. In this model the voltage is the solution of a Poisson equation in an infinite planar domain whose boundary is an array of circular pads of radius ", and we deal with the singular limit Ɛ → 0 case. In comparison with approximations that appear in the electronic engineering literature, our formula is more complete since we have obtained terms up to order Ɛ15. A procedure will be presented to compute all the successive terms, which can be interpreted as using multipole solutions of equations involving spatial derivatives of functions. To deduce the formula we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and of the Gauss constant G

Repeatability in automatic sorting of curved Norway spruce saw logs

Abstract

The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

LWC-paperin opasiteetin parantaminen

LWC-syväpainopaperilta vaaditaan hyvän ajettavuuden, kiillon ja sileyden ohella hyvää opasiteettia. Tämä on asettanut haasteita LWC-paperin valmistajille paperin neliömassojen laskiessa. Tässä diplomityössä etsittiin keinoja parantaa kevyiden LWC-syväpainolajien opasiteettia heikentämättä oleellisesti muita tärkeitä paperin ominaisuuksia. Tavoitteena oli nostaa CR48-lajin opasiteetti tavoitearvoon 90 %. Työn kirjallisuusosassa perehdyttiin paperin optisten ominaisuuksien teoriaan sekä raaka-aineisiin ja prosessin osiin, joilla on vaikutusta paperin opasiteettiin. Työn kokeellisessa osassa tutkittiin olemassa olevan aineiston perusteella tekijöitä, joilla uskottiin olevan vaikutusta CR48-lajin opasiteettiin. Tutkimuksen ja kirjallisuuden perusteella ajettiin tehdaskoeajoa, joiden avulla pyrittiin parantamaan paperin opasiteettia. CR48-lajin opasiteettitavoite saavutettiin kolmella eri tavalla. Opasiteettitavoite saavutettiin, kun paperin vaaleus säädettiin tavoitearvoon pigmenttivärin avulla tumman hierteen sijasta. Tällöin väripigmentin määrää päällystyspastassa nostettiin 0,01 osaa ja valkaistun hierteen osuus kokonaishierteen määrästä oli 100 %. Vaaleuden säätö pastavärillä oli käytännössä hidasta ja hankalaa. Opasiteettitavoite saavutettiin myös, kun hierre jauhettiin täysin koeterillä. Koeterillä tapahtuva jauhatus oli rajumpaa ja katkovampaa kuin perinteisillä terillä, joten hienoaineen lisääntyminen ja kuidun lyheneminen paransivat paperin opasiteettia, mutta lujuudet huononivat. Lisäksi tavoiteopasiteetti saavutettiin, kun sellun osuutta vähennettiin 8 %-yksikköä. Lujuuden säilymisen kannalta sellun vähennys oli parempi keino opasiteetin parantamiseksi kuin hierteen jauhaminen koeterillä. Koeajojen perusteella pohjapaperin tuhkapitoisuuden nostolla ja hierteen CSF-luvun alentamisella ei ollut vaikutusta paperin opasiteettiin. Lisäksi 100 %:nen koeterillä jauhettu sahahakehierre antoi paperille huonomman opasiteetin kuin hierre, josta puolet oli jauhettu koeterillä ja raaka-aineesta 25 % oli sahahaketta.

The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levels

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custombuilt optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

Formal Power Analysis of Systems-on-Chip

The design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.