Improving the efficiency of high power piezoelectric transducers for industrial applications

Most high-power ultrasound applications are driven by two-level inverters. However, the broad spectral content of the two-level pulse results in undesired harmonics that can decrease the performance of the system significantly. On the other hand, it is crucial to excite the piezoelectric devices at their main resonant frequency in order to have maximum energy conversion. Therefore a high-quality, low-distorted power signal is needed to excite the high-power piezoelectric transducer at its resonant frequency. This study proposes an efficient approach to develop the performance of high-power ultrasonic applications using multilevel inverters along with a frequency estimation algorithm. In this method, the resonant frequencies are estimated based on relative minimums of the piezoelectric impedance frequency response. The algorithm follows the resonant frequency variation and adapts the multilevel inverter reference frequency to drive an ultrasound transducer at high power. Extensive simulation and experimental results indicate the effectiveness of the proposed approach.

Five-level current-source inverters with buck-boost and inductive-current balancing capabilities

This paper presents new five-level current-source inverters (CSIs) with voltage/current buck-boost capability, unlike existing five-level CSIs where only voltage-boost operation is supported. The proposed inverters attain self-inductive-current-balancing per switching cycle at their dc front ends without having to include additional balancing hardware or complex control manipulation. The inverters can conveniently be controlled by using the well-established phase-shifted carrier modulation scheme with only two additional linear references and a mapping logic table needed. Existing modulators can therefore be conveniently retrofitted for controlling the presented inverters. By appropriately coordinating the inverter gating signals, their implementations can be realized by using the least number of components without degrading performance. These enhanced features of the inverters have already been verified in simulation and experimentally using a scaled-down laboratory platform.

A Combination of Hexagonal and 12-Sided Polygonal Voltage Space Vector PWM Control for IM Drives Using Cascaded Two-Level Inverters

This paper proposes a multilevel inverter configuration which produces a hexagonal voltage space vector structure in the lower modulation region and a 12-sided polygonal space vector structure in the overmodulation region. A conventional multilevel inverter produces 6n plusmn 1 (n = odd) harmonics in the phase voltage during overmodulation and in the extreme square-wave mode of operation. However, this inverter produces a 12-sided polygonal space vector location, leading to the elimination of 6n plusmn 1 (n = odd) harmonics in the overmodulation region extending to a final 12-step mode of operation with a smooth transition. The benefits of this arrangement are lower losses and reduced torque pulsation in an induction motor drive fed from this converter at higher modulation indexes. The inverter is fabricated by using three conventional cascaded two-level inverters with asymmetric dc-bus voltages. A comparative simulation study of the harmonic distortion in the phase voltage and associated losses in conventional multilevel inverters and that of the proposed inverter is presented in this paper. Experimental validation on a prototype shows that the proposed converter is suitable for high-power applications because of low harmonic distortion and low losses.

Fast response static var generator for improving the power system performance of an electric arc furnace (EAF)

Cascaded multilevel inverters-based Static Var Generators (SVGs) are FACTS equipment introduced for active and reactive power flow control. They eliminate the need for zigzag transformers and give a fast response. However, with regard to their application for flicker reduction in using Electric Arc Furnace (EAF), the existing multilevel inverter-based SVGs suffer from the following disadvantages. (1) To control the reactive power, an off-line calculation of Modulation Index (MI) is required to adjust the SVG output voltage. This slows down the transient response to the changes of reactive power; and (2) Random active power exchange may cause unbalance to the voltage of the d.c. link (HBI) capacitor when the reactive power control is done by adjusting the power angle d alone. To resolve these problems, a mathematical model of 11-level cascaded SVG, was developed. A new control strategy involving both MI (modulation index) and power angle (d) is proposed. A selected harmonics elimination method (SHEM) is taken for switching pattern calculations. To shorten the response time and simplify the controls system, feed forward neural networks are used for on-line computation of the switching patterns instead of using look-up tables. The proposed controller updates the MI and switching patterns once each line-cycle according to the sampled reactive power Qs. Meanwhile, the remainder reactive power (compensated by the MI) and the reactive power variations during the line-cycle will be continuously compensated by adjusting the power angles, d. The scheme senses both variables MI and d, and takes action through the inverter switching angle, qi. As a result, the proposed SVG is expected to give a faster and more accurate response than present designs allow. In support of the proposal there is a mathematical model for reactive powered distribution and a sensitivity matrix for voltage regulation assessment, MATLAB simulation results are provided to validate the proposed schemes. The performance with non-linear time varying loads is analysed and refers to a general review of flicker, of methods for measuring flickers due to arc furnace and means for mitigation.

A Medium-Voltage Inverter-Fed IM Drive Using Multilevel 12-Sided Polygonal Vectors, With Nearly Constant Switching Frequency Current Hysteresis Controller

In this paper, a current error space vector (CESV)-based hysteresis current controller for a multilevel 12-sided voltage space vector-based inverter-fed induction motor (IM) drive is proposed. The proposed controller gives a nearly constant switching frequency operation throughout different speeds in the linear modulation region. It achieves the elimination of 6n +/- 1, n = odd harmonics from the phase voltages and currents in the entire modulation range, with an increase in the linear modulation range. It also exhibits fast dynamic behavior under different transient conditions and has a simple controller implementation. Nearly constant switching frequency is obtained by matching the steady-state CESV boundaries of the proposed controller with that of a constant switching frequency SVPWM-based drive. In the proposed controller, the CESV reference boundaries are computed online, using the switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages. Vector change is decided by projecting the actual current error along the computed hysteresis space vector boundary of the presently applied vector. The estimated reference phase voltages are found from the stator current error ripple and the parameters of the IM.

Asymmetrical DC link voltage configuration for a diode-clamped inverter

There is a trade off between a number of output voltage levels and the reliability and efficiency of a multilevel converter. A new configuration of diode-clamped multilevel inverters with a different combination of DC link capacitors voltage has been proposed in this paper. Two different symmetrical and asymmetrical unequal arrangements for a four-level diode-clamped inverter have been compared, in order to find an optimum arrangement with lower switching losses and optimised output voltage quality. The simulation and hardware results for a four-level inverter show that the asymmetrical configuration can obtain more output voltage levels with the same number of components compared with a conventional four-level inverter and this will lead to the reduction of the harmonic content of the output voltage. A new family of multi-output DC-DC converters with a simple control strategy has been utilised as a front-end converter to supply the DC link capacitor voltages for the optimised configuration.

Multilevel converters in renewable energy systems

In photovoltaic, fuel cells and storage batteries, the low output DC voltage should be boosted. Therefore, a step-up converter is necessary to boost the low DC voltage for the DC link voltage of the inverter. The main contribution of this chapter is to electrical energy conversion in renewable energy systems based on multilevel inverters. Different configuration of renewable energy systems based on power converters will be discussed in detail. Finally, a new single inductor Multi-Output Boost (MOB) converter is proposed, which is compatible with the diode-clamped configuration. Steady state and dynamic analyses have been carried out in order to show the validity of the proposed topology. Then the joint circuit of the proposed DC-DC converter with a three-level diode-clamped converter is presented in order to have a series regulated voltage at the DC link voltage of the diode-clamped inverter. MOB converter can boost the low input DC voltage of the renewable energy sources and at the same time adjust the voltage across each capacitor to the desired voltage levels, thereby solving the main problem associated with capacitor voltage imbalance in this type of multilevel converter.

A new multilevel converter configuration for high power and high quality applications

The Queensland University of Technology (QUT) allows the presentation of theses for the Degree of Doctor of Philosophy in the format of published or submitted papers, where such papers have been published, accepted or submitted during the period of candidature. This thesis is composed of ten published /submitted papers and book chapters of which nine have been published and one is under review. This project is financially supported by an Australian Research Council (ARC) Discovery Grant with the aim of investigating multilevel topologies for high quality and high power applications, with specific emphasis on renewable energy systems. The rapid evolution of renewable energy within the last several years has resulted in the design of efficient power converters suitable for medium and high-power applications such as wind turbine and photovoltaic (PV) systems. Today, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements controlled by powerful processor systems. However, it is hard to connect the traditional converters to the high and medium voltage grids, as a single power switch cannot stand at high voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Besides this important feature, multilevel converters have the capability to generate stepped waveforms. Consequently, in comparison with conventional two-level inverters, they present lower switching losses, lower voltage stress across loads, lower electromagnetic interference (EMI) and higher quality output waveforms. These properties enable the connection of renewable energy sources directly to the grid without using expensive, bulky, heavy line transformers. Additionally, they minimize the size of the passive filter and increase the durability of electrical devices. However, multilevel converters have only been utilised in very particular applications, mainly due to the structural limitations, high cost and complexity of the multilevel converter system and control. New developments in the fields of power semiconductor switches and processors will favor the multilevel converters for many other fields of application. The main application for the multilevel converter presented in this work is the front-end power converter in renewable energy systems. Diode-clamped and cascade converters are the most common type of multilevel converters widely used in different renewable energy system applications. However, some drawbacks – such as capacitor voltage imbalance, number of components, and complexity of the control system – still exist, and these are investigated in the framework of this thesis. Various simulations using software simulation tools are undertaken and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results. This thesis is divided into two main sections. The first section focuses on solving the capacitor voltage imbalance for a wide range of applications, and on decreasing the complexity of the control strategy on the inverter side. The idea of using sharing switches at the output structure of the DC-DC front-end converters is proposed to balance the series DC link capacitors. A new family of multioutput DC-DC converters is proposed for renewable energy systems connected to the DC link voltage of diode-clamped converters. The main objective of this type of converter is the sharing of the total output voltage into several series voltage levels using sharing switches. This solves the problems associated with capacitor voltage imbalance in diode-clamped multilevel converters. These converters adjust the variable and unregulated DC voltage generated by renewable energy systems (such as PV) to the desirable series multiple voltage levels at the inverter DC side. A multi-output boost (MOB) converter, with one inductor and series output voltage, is presented. This converter is suitable for renewable energy systems based on diode-clamped converters because it boosts the low output voltage and provides the series capacitor at the output side. A simple control strategy using cross voltage control with internal current loop is presented to obtain the desired voltage levels at the output voltage. The proposed topology and control strategy are validated by simulation and hardware results. Using the idea of voltage sharing switches, the circuit structure of different topologies of multi-output DC-DC converters – or multi-output voltage sharing (MOVS) converters – have been proposed. In order to verify the feasibility of this topology and its application, steady state and dynamic analyses have been carried out. Simulation and experiments using the proposed control strategy have verified the mathematical analysis. The second part of this thesis addresses the second problem of multilevel converters: the need to improve their quality with minimum cost and complexity. This is related to utilising asymmetrical multilevel topologies instead of conventional multilevel converters; this can increase the quality of output waveforms with a minimum number of components. It also allows for a reduction in the cost and complexity of systems while maintaining the same output quality, or for an increase in the quality while maintaining the same cost and complexity. Therefore, the asymmetrical configuration for two common types of multilevel converters – diode-clamped and cascade converters – is investigated. Also, as well as addressing the maximisation of the output voltage resolution, some technical issues – such as adjacent switching vectors – should be taken into account in asymmetrical multilevel configurations to keep the total harmonic distortion (THD) and switching losses to a minimum. Thus, the asymmetrical diode-clamped converter is proposed. An appropriate asymmetrical DC link arrangement is presented for four-level diode-clamped converters by keeping adjacent switching vectors. In this way, five-level inverter performance is achieved for the same level of complexity of the four-level inverter. Dealing with the capacitor voltage imbalance problem in asymmetrical diodeclamped converters has inspired the proposal for two different DC-DC topologies with a suitable control strategy. A Triple-Output Boost (TOB) converter and a Boost 3-Output Voltage Sharing (Boost-3OVS) converter connected to the four-level diode-clamped converter are proposed to arrange the proposed asymmetrical DC link for the high modulation indices and unity power factor. Cascade converters have shown their abilities and strengths in medium and high power applications. Using asymmetrical H-bridge inverters, more voltage levels can be generated in output voltage with the same number of components as the symmetrical converters. The concept of cascading multilevel H-bridge cells is used to propose a fifteen-level cascade inverter using a four-level H-bridge symmetrical diode-clamped converter, cascaded with classical two-level Hbridge inverters. A DC voltage ratio of cells is presented to obtain maximum voltage levels on output voltage, with adjacent switching vectors between all possible voltage levels; this can minimize the switching losses. This structure can save five isolated DC sources and twelve switches in comparison to conventional cascade converters with series two-level H bridge inverters. To increase the quality in presented hybrid topology with minimum number of components, a new cascade inverter is verified by cascading an asymmetrical four-level H-bridge diode-clamped inverter. An inverter with nineteen-level performance was achieved. This synthesizes more voltage levels with lower voltage and current THD, rather than using a symmetrical diode-clamped inverter with the same configuration and equivalent number of power components. Two different predictive current control methods for the switching states selection are proposed to minimise either losses or THD of voltage in hybrid converters. High voltage spikes at switching time in experimental results and investigation of a diode-clamped inverter structure raised another problem associated with high-level high voltage multilevel converters. Power switching components with fast switching, combined with hard switched-converters, produce high di/dt during turn off time. Thus, stray inductance of interconnections becomes an important issue and raises overvoltage and EMI issues correlated to the number of components. Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. The effect of different transient current loops on busbar physical structure of the high-voltage highlevel diode-clamped converters is highlighted. Design considerations of proper planar busbar are also presented to optimise the overall design of diode-clamped converters.

Multilevel converter structure and control

In recent years, multilevel converters are becoming more popular and attractive than traditional converters in high voltage and high power applications. Multilevel converters are particularly suitable for harmonic reduction in high power applications where semiconductor devices are not able to operate at high switching frequencies or in high voltage applications where multilevel converters reduce the need to connect devices in series to achieve high switch voltage ratings. This thesis investigated two aspects of multilevel converters: structure and control. The first part of this thesis focuses on inductance between a DC supply and inverter components in order to minimise loop inductance, which causes overvoltages and stored energy losses during switching. Three dimensional finite element simulations and experimental tests have been carried out for all sections to verify theoretical developments. The major contributions of this section of the thesis are as follows: The use of a large area thin conductor sheet with a rectangular cross section separated by dielectric sheets (planar busbar) instead of circular cross section wires, contributes to a reduction of the stray inductance. A number of approximate equations exist for calculating the inductance of a rectangular conductor but an assumption was made that the current density was uniform throughout the conductors. This assumption is not valid for an inverter with a point injection of current. A mathematical analysis of a planar bus bar has been performed at low and high frequencies and the inductance and the resistance values between the two points of the planar busbar have been determined. A new physical structure for a voltage source inverter with symmetrical planar bus bar structure called Reduced Layer Planar Bus bar, is proposed in this thesis based on the current point injection theory. This new type of planar busbar minimises the variation in stray inductance for different switching states. The reduced layer planar busbar is a new innovation in planar busbars for high power inverters with minimum separation between busbars, optimum stray inductance and improved thermal performances. This type of the planar busbar is suitable for high power inverters, where the voltage source is supported by several capacitors in parallel in order to provide a low ripple DC voltage during operation. A two layer planar busbar with different materials has been analysed theoretically in order to determine the resistance of bus bars during switching. Increasing the resistance of the planar busbar can gain a damping ratio between stray inductance and capacitance and affects the performance of current loop during switching. The aim of this section is to increase the resistance of the planar bus bar at high frequencies (during switching) and without significantly increasing the planar busbar resistance at low frequency (50 Hz) using the skin effect. This contribution shows a novel structure of busbar suitable for high power applications where high resistance is required at switching times. In multilevel converters there are different loop inductances between busbars and power switches associated with different switching states. The aim of this research is to consider all combinations of the switching states for each multilevel converter topology and identify the loop inductance for each switching state. Results show that the physical layout of the busbars is very important for minimisation of the loop inductance at each switch state. Novel symmetrical busbar structures are proposed for multilevel converters with diode-clamp and flying-capacitor topologies which minimise the worst case in stray inductance for different switching states. Overshoot voltages and thermal problems are considered for each topology to optimise the planar busbar structure. In the second part of the thesis, closed loop current techniques have been investigated for single and three phase multilevel converters. The aims of this section are to investigate and propose suitable current controllers such as hysteresis and predictive techniques for multilevel converters with low harmonic distortion and switching losses. This section of the thesis can be classified into three parts as follows: An optimum space vector modulation technique for a three-phase voltage source inverter based on a minimum-loss strategy is proposed. One of the degrees of freedom for optimisation of the space vector modulation is the selection of the zero vectors in the switching sequence. This new method improves switching transitions per cycle for a given level of distortion as the zero vector does not alternate between each sector. The harmonic spectrum and weighted total harmonic distortion for these strategies are compared and results show up to 7% weighted total harmonic distortion improvement over the previous minimum-loss strategy. The concept of SVM technique is a very convenient representation of a set of three-phase voltages or currents used for current control techniques. A new hysteresis current control technique for a single-phase multilevel converter with flying-capacitor topology is developed. This technique is based on magnitude and time errors to optimise the level change of converter output voltage. This method also considers how to improve unbalanced voltages of capacitors using voltage vectors in order to minimise switching losses. Logic controls require handling a large number of switches and a Programmable Logic Device (PLD) is a natural implementation for state transition description. The simulation and experimental results describe and verify the current control technique for the converter. A novel predictive current control technique is proposed for a three-phase multilevel converter, which controls the capacitors' voltage and load current with minimum current ripple and switching losses. The advantage of this contribution is that the technique can be applied to more voltage levels without significantly changing the control circuit. The three-phase five-level inverter with a pure inductive load has been implemented to track three-phase reference currents using analogue circuits and a programmable logic device.

A new unequal DC link voltage configuration for a single phase multilevel converter to reduce low order harmonics

Multilevel converters are used in high power and high voltage applications due to their attractive benefits in generating high quality output voltage. Increasing the number of voltage levels can lead to a reduction in lower order harmonics. Various modulation and control techniques are introduced for multilevel converters like Space Vector Modulation (SVM), Sinusoidal Pulse Width Modulation (SPWM) and Harmonic Elimination (HE) methods. Multilevel converters may have a DC link with equal or unequal DC voltages. In this paper a new modulation technique based on harmonic elimination method is proposed for those multilevel converters that have unequal DC link voltages. This new technique has better effect on output voltage quality and less Total Harmonic Distortion (THD) than other modulation techniques. In order to verify the proposed modulation technique, MATLAB simulations are carried out for a single-phase diode-clamped inverter.

Harmonic quality of multilevel cascade inverters with random carrier phase pulse width modulation

The output harmonic quality of N series connected full-bridge dc-ac inverters is investigated. The inverters are pulse width modulated using a common reference signal but randomly phased carrier signals. Through analysis and simulation, probability distributions for inverter output harmonics and vector representations of N carrier phases are combined and assessed. It is concluded that a low total harmonic distortion is most likely to occur and will decrease further as N increases.

Harmonic quality of multilevel cascade inverters with random carrier phase pulse width modulation

The output harmonic quality of N series connected full-bridge dc-ac inverters is investigated. The inverters are pulse width modulated using a common reference signal but randomly phased carrier signals. Through analysis and simulation, probability distributions for inverter output harmonics and vector representations of N carrier phases are combined and assessed. It is concluded that a low total harmonic distortion is most likely to occur and will decrease further as N increases.

Cascade multilevel static synchronous compensator configuration for wind farms

Modulation and control of a cascade multilevel static synchronous compensator (STATCOM) configuration to improve the quality of voltage generated by wind power systems are presented. The proposed STATCOM configuration needs only four dc-link capacitors and 24 switches to synthesise nine-level operation. In addition to that, switching losses are further reduced by splitting the voltage source inverter of the STATCOM into two units called the `bulk inverter` and the `conditioning inverter`. The high-power bulk inverter is operated at low frequency whereas the low-power conditioning inverter is operated at high frequency to suppress harmonics produced by the bulk inverter. Fluctuations at the point of common coupling voltage, caused by sudden wind changes, are suppressed by controlling reactive power of the STATCOM. Simulation and experimental results are presented to verify the efficacy of the proposed modulation and control techniques used in the STATCOM.