Four group decodable differential scaled unitary linear space-time codes

Differential Unitary Space-Time Block codes (STBCs) offer a means to communicate on the Multiple Input Multiple Output (MIMO) channel without the need for channel knowledge at both the transmitter and the receiver. Recently Yuen-Guan-Tjhung have proposed Single-Symbol-Decodable Differential Space-Time Modulation based on Quasi-Orthogonal Designs (QODs) by replacing the original unitary criterion by a scaled unitary criterion. These codes were also shown to perform better than differential unitary STBCs from Orthogonal Designs (ODs). However the rate (as measured in complex symbols per channel use) of the codes of Yuen-Guan-Tjhung decay as the number of transmit antennas increase. In this paper, a new class of differential scaled unitary STBCs for all even number of transmit antennas is proposed. These codes have a rate of 1 complex symbols per channel use, achieve full diversity and moreover they are four-group decodable, i.e., the set of real symbols can be partitioned into four groups and decoding can be done for the symbols in each group separately. Explicit construction of multidimensional signal sets that yield full diversity for this new class of codes is also given.

Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor Drive Using Conventional Three Level Inverters

A novel dodecagonal space vector structure for induction motor drive is presented in this paper. It consists of two dodecagons, with the radius of the outer one twice the inner one. Compared to existing dodecagonal space vector structures, to achieve the same PWM output voltage quality, the proposed topology lowers the switching frequency of the inverters and reduces the device ratings to half. At the same time, other benefits obtained from existing dodecagonal space vector structure are retained here. This includes the extension of the linear modulation range and elimination of all 6+/-1 harmonics (n=odd) from the phase voltage. The proposed structure is realized by feeding an open-end winding induction motor with two conventional three level inverters. A detailed calculation of the PWM timings for switching the space vector points is also presented. Simulation and experimental results indicate the possible application of the proposed idea for high power drives.

BER analysis of space-time block codes from generalized complex orthogonal designs for M-PSK

In this paper, we present an analysis for the bit error rate (BER) performance of space-time block codes (STBC) from generalized complex orthogonal designs for M-PSK modulation. In STBCs from complex orthogonal designs (COD), the norms of the column vectors are the same (e.g., Alamouti code). However, in generalized COD (GCOD), the norms of the column vectors may not necessarily be the same (e.g., the rate-3/5 and rate-7/11 codes by Su and Xia in [1]). STBCs from GCOD are of interest because of the high rates that they can achieve (in [2], it has been shown that the maximum achievable rate for STBCs from GCOD is bounded by 4/5). While the BER performance of STBCs: from COD (e.g., Alamouti code) can be simply obtained from existing analytical expressions for receive diversity with the same diversity order by appropriately scaling the SNR, this can not be done for STBCs from GCOD (because of the unequal norms of the column vectors). Our contribution in this paper is that we derive analytical expressions for the BER performance of any STBC from GCOD. Our BER analysis for the GCOD captures the performance of STBCs from COD as special cases. We validate our results with two STBCs from GCOD reported by Su and Xia in [1], for 5 and 6 transmit antennas (G(5) and G(6) in [1]) with rates 7/11 and 3/5, respectively.

Improved switching frequency variation control of hysteresis controlled voltage source inverter-fed IM drives using current error space vector

A constant switching frequency current error space vector-based hysteresis controller for two-level voltage source inverter-fed induction motor (IM) drives is proposed in this study. The proposed controller is capable of driving the IM in the entire speed range extending to the six-step mode. The proposed controller uses the parabolic boundary, reported earlier, for vector selection in a sector, but uses simple, fast and self-adaptive sector identification logic for sector change detection in the entire modulation range. This new scheme detects the sector change using the change in direction of current error along the axes jA, jB and jC. Most of the previous schemes use an outer boundary for sector change detection. So the current error goes outside the boundary six times during sector change, in one cycle,, introducing additional fifth and seventh harmonic components in phase current. This may cause sixth harmonic torque pulsations in the motor and spread in the harmonic spectrum of phase voltage. The proposed new scheme detects the sector change fast and accurately eliminating the chance of introducing additional fifth and seventh harmonic components in phase current and provides harmonic spectrum of phase voltage, which exactly matches with that of constant switching frequency voltage-controlled space vector pulse width modulation (VC-SVPWM)-based two-level inverter-fed drives.

BER analysis of space-time block codes from generalized complex orthogonal designs for M-PSK

In this paper, we present an analysis for the bit error rate (BER) performance of space-time block codes (STBC) from generalized complex orthogonal designs for M-PSK modulation. In STBCs from complex orthogonal designs (COD), the norms of the column vectors are the same (e.g., Alamouti code). However, in generalized COD (GCOD), the norms of the column vectors may not necessarily be the same (e.g., the rate-3/5 and rate-7/11 codes by Su and Xia in [1]). STBCs from GCOD are of interest because of the high rates that they can achieve (in [2], it has been shown that the maximum achievable rate for STBCs from GCOD is bounded by 4/5). While the BER performance of STBCs: from COD (e.g., Alamouti code) can be simply obtained from existing analytical expressions for receive diversity with the same diversity order by appropriately scaling the SNR, this can not be done for STBCs from GCOD (because of the unequal norms of the column vectors). Our contribution in this paper is that we derive analytical expressions for the BER performance of any STBC from GCOD. Our BER analysis for the GCOD captures the performance of STBCs from COD as special cases. We validate our results with two STBCs from GCOD reported by Su and Xia in [1], for 5 and 6 transmit antennas (G(5) and G(6) in [1]) with rates 7/11 and 3/5, respectively.

BER analysis of space-time block codes from generalized complex orthogonal designs for M-PSK

In this paper, we present an analysis for the bit error rate (BER) performance of space-time block codes (STBC) from generalized complex orthogonal designs for M-PSK modulation. In STBCs from complex orthogonal designs (COD), the norms of the column vectors are the same (e.g., Alamouti code). However, in generalized COD (GCOD), the norms of the column vectors may not necessarily be the same (e.g., the rate-3/5 and rate-7/11 codes by Su and Xia in [1]). STBCs from GCOD are of interest because of the high rates that they can achieve (in [2], it has been shown that the maximum achievable rate for STBCs from GCOD is bounded by 4/5). While the BER performance of STBCs: from COD (e.g., Alamouti code) can be simply obtained from existing analytical expressions for receive diversity with the same diversity order by appropriately scaling the SNR, this can not be done for STBCs from GCOD (because of the unequal norms of the column vectors). Our contribution in this paper is that we derive analytical expressions for the BER performance of any STBC from GCOD. Our BER analysis for the GCOD captures the performance of STBCs from COD as special cases. We validate our results with two STBCs from GCOD reported by Su and Xia in [1], for 5 and 6 transmit antennas (G(5) and G(6) in [1]) with rates 7/11 and 3/5, respectively.

Dodecagonal space vector diagram using cascaded H-Bridge inverters

This paper proposes the development of dodecagonal (12-sided) space vector diagrams from cascaded H-Bridge inverters. As already reported in literatures, dodecagonal space vector diagrams have many advantages over conventional hexagonal ones. Some of them include the absence of 6n±1, (n=odd) harmonics from the phase voltage, and the extension of the linear modulation range. In this paper, a new power circuit is proposed for generating multiple dodecagons in the space vector plane. It consists of two cascaded H-Bridge cells fed from asymmetric dc voltage sources. It is shown that, with proper PWM timing calculation and placement of active and zero vectors, a very high quality of sine-wave can be produced. At the same time, the switching frequency of individual cells can be reduced substantially. Detailed PWM analysis, one design example and an elaborate simulation study is presented to support the proposed idea.

Novel Switching Sequences for a Space-Vector-Modulated Three-Level Inverter

A three-level inverter produces six active vectors, each of normalized magnitudes 1, 0.866, and 0.5, besides a zero vector. The vectors of relative length 0.5 are termed pivot vectors.The three nearest voltage vectors are usually used to synthesize the reference vector. In most continuous pulsewidth-modulation(PWM) schemes, the switching sequence begins from a pivot vector and ends with the same pivot vector. Thus, the pivot vector is applied twice in a subcycle or half-carrier cycle. This paper proposes and investigates alternative switching sequences, which use the pivot vector only once but employ one of the other two vectors twice within the subcycle. The total harmonic distortion(THD) in the fundamental line current pertaining to these novel sequences is studied theoretically as well as experimentally over the whole range of modulation. Compared with centered space vector PWM, two of the proposed sequences lead to reduced THD at high modulation indices at a given average switching frequency.

Space vector based bus clamped PWM algorithms for three level inverters: implementation, performance analysis and application considerations

This paper describes the different types of space vector based bus clamped PWM algorithms for three level inverters. A novel bus clamp PWM algorithm for low modulation indices region is also presented. The principles and switching sequences of all the types of bus clamped algorithms for high switching frequency are presented. Synchronized version of the PWM sequences for high power applications where switching frequency is low is also presented. The implementation details on DSP based digital controller and experimental results are presented. The THD of the output waveforms is studied for the entire operating region and is compared with the conventional space vector PWM technique. The bus clamped techniques can be used to reduce the switching losses or to improve the output voltage quality or both.. Different issues dominate depending on the type of application and power rating of the inverters. The results presented in this paper can be used for judicious use of the PWM techniques, which result in improved system efficiency and performance.

Experimental Investigation on the Effect of Advanced Bus-Clamping Pulsewidth Modulation on Motor Acoustic Noise

Voltage source inverters (VSIs) supply nonsinusoidal voltages to induction motor drives, leading to line current distortion and torque pulsation. Conventional space vector pulsewidth modulation (PWM) techniques are widely used in VSIs on the account of good waveform quality and high dc bus utilization. In a conventional space vector PWM technique, the switching sequence begins with one zero state and ends with the other zero state in a subcycle. Some novel switching sequences have been proposed, which employ only one zero state but apply one of the two active states twice in a subcycle. One pair of such special switching sequences has recently been shown to reduce the pulsating torque considerably. In this paper, the conventional and special switching sequences are compared experimentally in terms of acoustic noise. In the low-and medium-speed ranges, the special switching sequence is seen to reduce the amplitude of the tonal component of noise at the switching frequency considerably and is also found to result in spread spectrum.

Multilevel dodecagonal space-vector generation for induction motor drives by cascading three-level and two-level inverters

This study proposes an inverter circuit topology capable of generating multilevel dodecagonal (12-sided polygon) voltage space vectors by the cascaded connection of two-level and three-level inverters. By the proper selection of DC-link voltages and resultant switching states for the inverters, voltage space vectors whose tips lie on three concentric dodecagons, are obtained. A rectifier circuit for the inverter is also proposed, which significantly improves the power factor. The topology offers advantages such as the complete elimination of the fifth and seventh harmonics in phase voltages and an extension of the linear modulation range. In this study, a simple method for the calculation of pulse width modulation timing was presented along with extensive simulation and experimental results in order to validate the proposed concept.

Multilevel Dodecagonal Voltage Space Vector Generation using Flying Capacitor topology for Induction motor drives

In this paper, a multilevel flying capacitor inverter topology suitable for generating multilevel dodecagonal space vectors for an induction motor drive, is proposed. Because of the dodecagonal space vectors, it has increased modulation range with the absence of all 6n +/- 1, (n=odd) harmonics in the phase voltage and currents. The topology, realized by flying capacitor three level inverters feeding an open-end winding induction motor, does not suffer the neutral point voltage imbalance issues seen in NPC inverters and the capacitors have inherent charge-balancing capability with PWM control using switching state redundancies. Furthermore, the proposed technique uses lesser number of power supplies compared to cascaded H-bridge or NPC based dodecagonal schemes and has better ride-through capability. Finally, the voltage control is obtained through a simple carrier-based space vector PWM scheme implemented on a DSP.

A Space-Vector-Based Hysteresis Current Controller for a General n-Level Inverter-Fed Drive With Nearly Constant Switching Frequency Control

A current-error space-vector-based hysteresis current controller for a general n-level voltage-source inverter (VSI)-fed three-phase induction motor (IM) drive is proposed here, with control of the switching frequency variation for the full linear modulation range. The proposed current controller monitors the space-vector-based current error of an n-level VSI-fed IM to keep the current error within a parabolic boundary, using the information of the current triangular sector in which the tip of the reference vector lies. Information of the reference voltage vector is estimated using the measured current-error space vectors, along the alpha- and beta-axes. Appropriate dimension and orientation of this parabolic boundary ensure a switching frequency spectrum similar to that of a constant-switching-frequency voltage-controlled space vector pulsewidth modulation (PWM) (SVPWM)-based IM drive. Like SVPWM for multilevel inverters, the proposed controller selects inverter switching vectors, forming a triangular sector in which the tip of the reference vector stays, for the hysteresis PWM control. The sector in the n-level inverter space vector diagram, in which the tip of the fundamental stator voltage stays, is precisely detected, using the sampled reference space vector estimated from the instantaneous current-error space vectors. The proposed controller retains all the advantages of a conventional hysteresis controller such as fast current control, with smooth transition to the overmodulation region. The proposed controller is implemented on a five-level VSI-fed 7.5-kW IM drive.

A Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage IM Drives

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n +/- 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including over-modulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally.

Medium Voltage Drive for Induction Motors Using Multilevel Octadecagonal Voltage Space Vectors

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept.