BITalino: a novel hardware framework for physiological computing

Physical computing has spun a true global revolution in the way in which the digital interfaces with the real world. From bicycle jackets with turn signal lights to twitter-controlled christmas trees, the Do-it-Yourself (DiY) hardware movement has been driving endless innovations and stimulating an age of creative engineering. This ongoing (r)evolution has been led by popular electronics platforms such as the Arduino, the Lilypad, or the Raspberry Pi, however, these are not designed taking into account the specific requirements of biosignal acquisition. To date, the physiological computing community has been severely lacking a parallel to that found in the DiY electronics realm, especially in what concerns suitable hardware frameworks. In this paper, we build on previous work developed within our group, focusing on an all-in-one, low-cost, and modular biosignal acquisition hardware platform, that makes it quicker and easier to build biomedical devices. We describe the main design considerations, experimental evaluation and circuit characterization results, together with the results from a usability study performed with volunteers from multiple target user groups, namely health sciences and electrical, biomedical, and computer engineering. Copyright © 2014 SCITEPRESS - Science and Technology Publications. All rights reserved.

Run-time defragmentation for dynamically reconfigurable hardware

Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains. However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused. A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.

BoaVista – Sensor Dedicado de Visão Artificial Baseado em Hardware (Re)configurável

4º Festival Nacional de Robótica - Actas do Encontro Científico - Proceedings of the Scientific Meeting, Biblioteca Almeida Garrett, Palácio de Cristal – Porto, 23-24 Abril 2004

Conceção de um tutorial de Iniciação ao co-projeto de Hardware/software

A crescente evolução dos dispositivos contendo circuitos integrados, em especial os FPGAs (Field Programmable Logic Arrays) e atualmente os System on a chip (SoCs) baseados em FPGAs, juntamente com a evolução das ferramentas, tem deixado um espaço entre o lançamento e a produção de materiais didáticos que auxiliem os engenheiros no Co- Projecto de hardware/software a partir dessas tecnologias. Com o intuito de auxiliar na redução desse intervalo temporal, o presente trabalho apresenta o desenvolvimento de documentos (tutoriais) direcionados a duas tecnologias recentes: a ferramenta de desenvolvimento de hardware/software VIVADO; e o SoC Zynq-7000, Z-7010, ambos desenvolvidos pela Xilinx. Os documentos produzidos são baseados num projeto básico totalmente implementado em lógica programável e do mesmo projeto implementado através do processador programável embarcado, para que seja possível avaliar o fluxo de projeto da ferramenta para um projeto totalmente implementado em hardware e o fluxo de projeto para o mesmo projeto implementado numa estrutura de harware/software.

Controller implementation using analog reconfigurable hardware (FPAA)

This Thesis has the main target to make a research about FPAA/dpASPs devices and technologies applied to control systems. These devices provide easy way to emulate analog circuits that can be reconfigurable by programming tools from manufactures and in case of dpASPs are able to be dynamically reconfigurable on the fly. It is described different kinds of technologies commercially available and also academic projects from researcher groups. These technologies are very recent and are in ramp up development to achieve a level of flexibility and integration to penetrate more easily the market. As occurs with CPLD/FPGAs, the FPAA/dpASPs technologies have the target to increase the productivity, reducing the development time and make easier future hardware reconfigurations reducing the costs. FPAA/dpAsps still have some limitations comparing with the classic analog circuits due to lower working frequencies and emulation of complex circuits that require more components inside the integrated circuit. However, they have great advantages in sensor signal condition, filter circuits and control systems. This thesis focuses practical implementations of these technologies to control system PID controllers. The result of the experiments confirms the efficacy of FPAA/dpASPs on signal condition and control systems.

Iron Overload in a Murine Model of Hereditary Hemochromatosis Is Associated with Accelerated Progression of Osteoarthritis Under Mechanical Stress

OBJECTIVE: Hereditary hemochromatosis (HH) is a disease caused by mutations in the Hfe gene characterised by systemic iron overload and associated with an increased prevalence of osteoarthritis (OA) but the role of iron overload in the development of OA is still undefined. To further understand the molecular mechanisms involved we have used a murine model of HH and studied the progression of experimental OA under mechanical stress. DESIGN: OA was surgically induced in the knee joints of 10-week-old C57BL6 (wild-type) mice and Hfe-KO mice. OA progression was assessed using histology, micro CT, gene expression and immunohistochemistry at 8 weeks after surgery. RESULTS: Hfe-KO mice showed a systemic iron overload and an increased iron accumulation in the knee synovial membrane following surgery. The histological OA score was significantly higher in the Hfe-KO mice at 8 weeks after surgery. Micro CT study of the proximal tibia revealed increased subchondral bone volume and increased trabecular thickness. Gene expression and immunohistochemical analysis showed a significant increase in the expression of matrix metallopeptidase 3 (MMP-3) in the joints of Hfe-KO mice compared with control mice at 8 weeks after surgery. CONCLUSIONS: HH was associated with an accelerated development of OA in mice. Our findings suggest that synovial iron overload has a definite role in the progression of HH-related OA

Conceção e implementação de um ambiente de baixo custo para processamento de imagens tomográficas

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

Secular trends in Klebsiella pneumoniae isolated in a tertiary-care hospital: increasing prevalence and accelerated decline in antimicrobial susceptibility

Abstract: INTRODUCTION Klebsiella pneumoniae has become an increasingly important etiologic agent of nosocomial infections in recent years. This is mainly due to the expression of virulence factors and development of resistance to several antimicrobial drugs. METHODS This retrospective study examines data obtained from the microbiology laboratory of a Brazilian tertiary-care hospital. To assess temporal trends in prevalence and antimicrobial susceptibility, K. pneumoniae isolates were analyzed from 2000 to 2013. The relative frequencies of K. pneumoniae isolation were calculated among all Gram-negative bacilli isolated in each period analyzed. Susceptibility tests were performed using automated systems. RESULTS: From 2000-2006, K. pneumonia isolates comprised 10.7% of isolated Gram-negative bacilli (455/4260). From 2007-2013, this percentage was 18.1% (965/5331). Strictly considering isolates from bloodstream infections, the relative annual prevalence of K. pneumoniae increased from 14-17% to 27-32% during the same periods. A progressive decrease in K. pneumoniae susceptibility to all antimicrobial agents assessed was detected. Partial resistance was also observed to antimicrobial drugs that have been used more recently, such as colistin and tigecycline. CONCLUSIONS Our study indicates that K. pneumoniae has become a major pathogen among hospitalized patients and confirms its recent trend of increasing antimicrobial resistance.

Measuring end-to-end delay in real-time auralisation systems

One of the major challenges in the development of an immersive system is handling the delay between the tracking of the user’s head position and the updated projection of a 3D image or auralised sound, also called end-to-end delay. Excessive end-to-end delay can result in the general decrement of the “feeling of presence”, the occurrence of motion sickness and poor performance in perception-action tasks. These latencies must be known in order to provide insights on the technological (hardware/software optimization) or psychophysical (recalibration sessions) strategies to deal with them. Our goal was to develop a new measurement method of end-to-end delay that is both precise and easily replicated. We used a Head and Torso simulator (HATS) as an auditory signal sensor, a fast response photo-sensor to detect a visual stimulus response from a Motion Capture System, and a voltage input trigger as real-time event. The HATS was mounted in a turntable which allowed us to precisely change the 3D sound relative to the head position. When the virtual sound source was at 90º azimuth, the correspondent HRTF would set all the intensity values to zero, at the same time a trigger would register the real-time event of turning the HATS 90º azimuth. Furthermore, with the HATS turned 90º to the left, the motion capture marker visualization would fell exactly in the photo-sensor receptor. This method allowed us to precisely measure the delay from tracking to displaying. Moreover, our results show that the method of tracking, its tracking frequency, and the rendering of the sound reflections are the main predictors of end-to-end delay.

Implementação de sistemas de encriptação AES advanced encryption standard em hardware para segurança

Dissertação de mestrado integrado em Engenharia Electrónica Industrial e Computadores

Projecto de hardware digital orientado por objectos

Os limites entre os domínios do software e do hardware são cada vez mais ténues, pelo que técnicas inicialmente experimentadas no software têm vindo a ser gradualmente aplicadas no hardware. Este artigo pretende descrever o estado actual da utilização da tecnologia de programação orientada por objectos no projecto de hardware digital. São analisadas as vantagens e implicações quando se introduzem conceitos ligados à tecnologia orientada por objectos em projectos de hardware e é apresentado um exemplo utilizando uma das extensões orientadas por objectos da linguagem VHDL.

Automatisierte Hardware-Software Partitionierung am Beispiel eines eingebetteten, echtzeitfähigen Stereobildanalysesystems in Kraftfahrzeugen

Hardware-Software Co-Design, Simulated Annealing, Real-Time Image Processing, Automated Hardware-Software Partitioning

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.