FPGA-based architecture for hyperspectral unmixing

This paper proposes an FPGA-based architecture for onboard hyperspectral unmixing. This method based on the Vertex Component Analysis (VCA) has several advantages, namely it is unsupervised, fully automatic, and it works without dimensionality reduction (DR) pre-processing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq-7020 SoC FPGA based on the Artix-7 FPGA programmable logic and tested using real hyperspectral datasets. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low cost embedded systems.

An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems’ CPUs. The security operations are performed by the hosts’ central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 μs to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.

Estado da Arte da Computação Evolutiva Aplicada à Eletrónica

A Computação Evolutiva enquadra-se na área da Inteligência Artificial e é um ramo das ciências da computação que tem vindo a ser aplicado na resolução de problemas em diversas áreas da Engenharia. Este trabalho apresenta o estado da arte da Computação Evolutiva, assim como algumas das suas aplicações no ramo da eletrónica, denominada Eletrónica Evolutiva (ou Hardware Evolutivo), enfatizando a síntese de circuitos digitais combinatórios. Em primeiro lugar apresenta-se a Inteligência Artificial, passando à Computação Evolutiva, nas suas principais vertentes: os Algoritmos Evolutivos baseados no processo da evolução das espécies de Charles Darwin e a Inteligência dos Enxames baseada no comportamento coletivo de alguns animais. No que diz respeito aos Algoritmos Evolutivos, descrevem-se as estratégias evolutivas, a programação genética, a programação evolutiva e com maior ênfase, os Algoritmos Genéticos. Em relação à Inteligência dos Enxames, descreve-se a otimização por colônia de formigas e a otimização por enxame de partículas. Em simultâneo realizou-se também um estudo da Eletrónica Evolutiva, explicando sucintamente algumas das áreas de aplicação, entre elas: a robótica, as FPGA, o roteamento de placas de circuito impresso, a síntese de circuitos digitais e analógicos, as telecomunicações e os controladores. A título de concretizar o estudo efetuado, apresenta-se um caso de estudo da aplicação dos algoritmos genéticos na síntese de circuitos digitais combinatórios, com base na análise e comparação de três referências de autores distintos. Com este estudo foi possível comparar, não só os resultados obtidos por cada um dos autores, mas também a forma como os algoritmos genéticos foram implementados, nomeadamente no que diz respeito aos parâmetros, operadores genéticos utilizados, função de avaliação, implementação em hardware e tipo de codificação do circuito.

Comportamento estrutural de ligações em painéis de cement bonded particle boards

Dissertação para obtenção do Grau de Mestre em Engenharia Civil, Perfil de Estruturas

Characterization tests for insulation boards made from corn cob and natural glues

In recent years there has been a growing interest in developing news solutions for more ecologic and efficient construction, including natural, renewable and local materials, thus contributing in the search for more efficient, economic and environmentally friendly construction. Several authors have assessed the possibility of using various agricultural sub products or wastes, as part of the effort of the scientific community to find alternative and more ecologic construction materials. Corn cob is an agricultural waste from a very important worldwide crop. Natural glues are made from natural materials, non-mineral, that can be used as such or after some modifications to achieve the behaviour and performance required. Two examples of these natural glues are casein and wheat flour-based glues that were used in the present study. Boards with different compositions were manufactured, having as variables the type of glue, the dimension of the corn cob particles and the features of the pressing process. The tests boards were characterized with physical and mechanical tests, such as thermal conductivity (λ) with a ISOMET 2104 and 60 mm diameter contact probe, density (ρ) based on EN 1602:2013, surface hardness (SH) with a PCE Shore A durometer, surface resistance (SR) with a PROCEQ PT pendular sclerometer, bending behaviour (σ) based on EN 12089:2013, compression behaviour (σ10) based on EN 826:2013 and resilience (R) based on EN 1094-1:2008, with a Zwick Rowell bending equipment with 2 kN and 50 kN load cells (Fig. 1), dynamic modulus of elasticity (Ed) with a Zeus Resonance Meter equipment (Fig. 5) based on NP EN 14146:2006 and water vapour permeability (δ) based on EN 12086:2013. The various boards produced were characterized according to the tests and the ones with the best results were C8_c8 (casein glue, grain size 2,38-4,76 mm, cold pressing for 8 hours), C8_c4 (casein glue, grain size 2,38-4,76 mm, cold pressing for 4 hours), F8_h0.5 (wheat flour glue, grain size 2,38-4,76 mm, hot pressing for 0,5 hours), FEV8_h0.5 (wheat flour, egg white and vinegar glue, grain size 2,38-4,76 mm, hot pressing for 0,5 hours) and FEVH68_c4 (wheat flour, egg white, vinegar and 6 g of sodium hydroxide glue, grain size 2,38-4,76 mm, cold pressing for 4 hours). Taking into account the various boards produced and respective test results the type of glue and the pressure and pressing time are very important factors which strongly influence the final product. The results obtained confirmed the initial hypotheses that these boards have potential as a thermal and, eventually, acoustic insulation material, to use as coating or intermediate layer on walls, floors or false ceilings. This type of board has a high mechanical resistance when compared with traditional insulating materials.The integrity of these boards seems to be maintained even in higher humidity environments. However, due to biological susceptibility and sensitivity to water, they would be more adequate for application in dry interior conditions.

FPGA field oriented control of an axial flux motor-in-wheel

This paper presents the design and the prototype implementation of a three-phase power inverter developed to drive a motor-in-wheel. The control system is implemented in a FPGA (Field Programmable Gate Array) device. The paper describes the Field Oriented Control (FOC) algorithm and the Space Vector Modulation (SVM) technique that were implemented. The control platform uses a Spartan-3E FPGA board, programmed with Verilog language. Simulation and experimental results are presented to validate the developed system operation under different load conditions. Finally are presented conclusions based on the experimental results.

Controlador com FPGA para um motor-in-wheel CA de fluxo axial

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e de Computadores

Hybrid hypervisor partially deployed on FPGA

Tese de Doutoramento em Engenharia Eletrónica e Computadores.

Aceleración de Algoritmos en Procesadores Multicore, GPGPU y FPGA. Algorithm Acceleration with Multicore, GPGPU and FPGA Processors.

El avance en la potencia de cómputo en nuestros días viene dado por la paralelización del procesamiento, dadas las características que disponen las nuevas arquitecturas de hardware. Utilizar convenientemente este hardware impacta en la aceleración de los algoritmos en ejecución (programas). Sin embargo, convertir de forma adecuada el algoritmo en su forma paralela es complejo, y a su vez, esta forma, es específica para cada tipo de hardware paralelo. En la actualidad los procesadores de uso general más comunes son los multicore, procesadores paralelos, también denominados Symmetric Multi-Processors (SMP). Hoy en día es difícil hallar un procesador para computadoras de escritorio que no tengan algún tipo de paralelismo del caracterizado por los SMP, siendo la tendencia de desarrollo, que cada día nos encontremos con procesadores con mayor numero de cores disponibles. Por otro lado, los dispositivos de procesamiento de video (Graphics Processor Units - GPU), a su vez, han ido desarrollando su potencia de cómputo por medio de disponer de múltiples unidades de procesamiento dentro de su composición electrónica, a tal punto que en la actualidad no es difícil encontrar placas de GPU con capacidad de 200 a 400 hilos de procesamiento paralelo. Estos procesadores son muy veloces y específicos para la tarea que fueron desarrollados, principalmente el procesamiento de video. Sin embargo, como este tipo de procesadores tiene muchos puntos en común con el procesamiento científico, estos dispositivos han ido reorientándose con el nombre de General Processing Graphics Processor Unit (GPGPU). A diferencia de los procesadores SMP señalados anteriormente, las GPGPU no son de propósito general y tienen sus complicaciones para uso general debido al límite en la cantidad de memoria que cada placa puede disponer y al tipo de procesamiento paralelo que debe realizar para poder ser productiva su utilización. Los dispositivos de lógica programable, FPGA, son dispositivos capaces de realizar grandes cantidades de operaciones en paralelo, por lo que pueden ser usados para la implementación de algoritmos específicos, aprovechando el paralelismo que estas ofrecen. Su inconveniente viene derivado de la complejidad para la programación y el testing del algoritmo instanciado en el dispositivo. Ante esta diversidad de procesadores paralelos, el objetivo de nuestro trabajo está enfocado en analizar las características especificas que cada uno de estos tienen, y su impacto en la estructura de los algoritmos para que su utilización pueda obtener rendimientos de procesamiento acordes al número de recursos utilizados y combinarlos de forma tal que su complementación sea benéfica. Específicamente, partiendo desde las características del hardware, determinar las propiedades que el algoritmo paralelo debe tener para poder ser acelerado. Las características de los algoritmos paralelos determinará a su vez cuál de estos nuevos tipos de hardware son los mas adecuados para su instanciación. En particular serán tenidos en cuenta el nivel de dependencia de datos, la necesidad de realizar sincronizaciones durante el procesamiento paralelo, el tamaño de datos a procesar y la complejidad de la programación paralela en cada tipo de hardware. Today´s advances in high-performance computing are driven by parallel processing capabilities of available hardware architectures. These architectures enable the acceleration of algorithms when thes ealgorithms are properly parallelized and exploit the specific processing power of the underneath architecture. Most current processors are targeted for general pruposes and integrate several processor cores on a single chip, resulting in what is known as a Symmetric Multiprocessing (SMP) unit. Nowadays even desktop computers make use of multicore processors. Meanwhile, the industry trend is to increase the number of integrated rocessor cores as technology matures. On the other hand, Graphics Processor Units (GPU), originally designed to handle only video processing, have emerged as interesting alternatives to implement algorithm acceleration. Current available GPUs are able to implement from 200 to 400 threads for parallel processing. Scientific computing can be implemented in these hardware thanks to the programability of new GPUs that have been denoted as General Processing Graphics Processor Units (GPGPU).However, GPGPU offer little memory with respect to that available for general-prupose processors; thus, the implementation of algorithms need to be addressed carefully. Finally, Field Programmable Gate Arrays (FPGA) are programmable devices which can implement hardware logic with low latency, high parallelism and deep pipelines. Thes devices can be used to implement specific algorithms that need to run at very high speeds. However, their programmability is harder that software approaches and debugging is typically time-consuming. In this context where several alternatives for speeding up algorithms are available, our work aims at determining the main features of thes architectures and developing the required know-how to accelerate algorithm execution on them. We look at identifying those algorithms that may fit better on a given architecture as well as compleme

Development of a semi-automatic self learning pattern recognition system for the control of electronic boards

This project was funded under the Applied Research Grants Scheme administered by Enterprise Ireland. The project was a partnership between Galway - Mayo Institute of Technology and an industrial company, Tyco/Mallinckrodt Galway. The project aimed to develop a semi - automatic, self - learning pattern recognition system capable of detecting defects on the printed circuits boards such as component vacancy, component misalignment, component orientation, component error, and component weld. The research was conducted in three directions: image acquisition, image filtering/recognition and software development. Image acquisition studied the process of forming and digitizing images and some fundamental aspects regarding the human visual perception. The importance of choosing the right camera and illumination system for a certain type of problem has been highlighted. Probably the most important step towards image recognition is image filtering, The filters are used to correct and enhance images in order to prepare them for recognition. Convolution, histogram equalisation, filters based on Boolean mathematics, noise reduction, edge detection, geometrical filters, cross-correlation filters and image compression are some examples of the filters that have been studied and successfully implemented in the software application. The software application developed during the research is customized in order to meet the requirements of the industrial partner. The application is able to analyze pictures, perform the filtering, build libraries, process images and generate log files. It incorporates most of the filters studied and together with the illumination system and the camera it provides a fully integrated framework able to analyze defects on printed circuit boards.

Untersuchung und Entwicklung von Algorithmen zur Stereobildauswertung für die Erfassung von Objekten im Umfeld von Fahrzeugen und Realisierung einer Hindernisdetektion in Echtzeit mittels einer Hardwareimplementierung auf einem FPGA

Magdeburg, Univ., Fak. für Elektrotechnik und Informationstechnik, Diss., 2009

Entwicklung einer FPGA-basierten NQR-Konsole

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Desenvolupament d'interfícies HW per a FPGA des de Matlab

Aquest projecte consisteix en el desenvolupament d’estructures hardware digitals, sintetitzables sobre FPGA i realitzades des d’un entorn gràfic de disseny a nivell de sistema (alt nivell). S'ha escollit el Simulink (entorn gràfic que treballa sobre el software matemàtic Matlab de Mathworks) com a entorn de disseny, i que gràcies a la interfície proporcionada per Altera (DSPBuilder) és capaç de generar codi VHDL sintetitzable. Concretament ens centrarem en la gestió d’un sistema capturador d'imatges de comptadors del cabal d'aigua, en el qual volem fer la caracterització del comptador. Aquest capturador consta bàsicament d'un sensor d'imatge i una FPGA. En aquesta caracterització el que es pretén es ajustar els diferents paràmetres del sistema per fer que la lectura sigui òptima per a cada model de comptador que existeixen al mercat, com ara l'exposició del sensor, el guany d'un color, la realització d'un filtrat de la imatge, etc.

Disseny d'un sistema HW/SW de control remot amb dispositius FPGA

El projecte que es presenta a continuació, té com a objectiu implementar un sistema HW/SW encastat en una FPGA, capaç d’executar funcions de control remot per infraroig en plataformes de televisió flexibles de Sony Corp. El disseny obtingut, s’incorporarà a un sistema més ampli de verificació i test de circuits impresos, dins del marc de producció SMD. La finalitat d’aquest projecte, és la realització d’un sistema flexible per a la implementació de comandaments de comunicació per infraroig amb circuits impresos. Prèviament, s’ha estudiat els conceptes bàsics referents a la implementació de sistemes amb FPGAs, la seva metodologia de desenvolupament i les principals característiques de la seva arquitectura. Com a especificacions, s’ha utilitzat l’estàndard de control remot per infraroig de Sony Corp SIRCS (Sony Infrared remote control system).

Desarrollo de un sistema integrado de navegación inercial: interfície IMU + FPGA

Els sistemes automatitzats que requereixen d’un control d’estabilitat o moviment es poden trobar cada cop en més àmbits. Aplicacions UAV o de posicionament global són les més comunes per aquest tipus de sistemes, degut a que necessiten d’un control de moviment molt precís. Per a dur a terme aquest procés s’utilitzen unitats de mesura inercial, que mitjançant acceleròmetres i giroscopis degudament posicionats, a més a més d’una correcció del possible error que puguin introduir aquests últims, proporcionen una acceleració i una velocitat angular de les quals es pot extreure el camí efectuat per aquestes unitats. La IMU, combinada amb un GPS i mitjançant un filtre de Kalman, proporcionen una major exactitud , a més d’un punt de partida (proporcionat per el GPS), un recorregut representable en un mapa y, en el cas de perdre la senyal GPS, poder seguir adquirint dades de la IMU. Aquestes dades poden ser recollides i processades per una FPGA, que a la vegada podem sincronitzar amb una PDA per a que l’usuari pugui veure representat el moviment del sistema. Aquest treball es centra en el funcionament de la IMU i l’adquisició de dades amb la FPGA. També introdueix el filtre de Kalman per a la correcció de l’error dels sensors.