A framework for mixed-criticality partitioned real-time embedded systems

Los sistemas empotrados son cada d��a m��s comunes y complejos, de modo que encontrar procesos seguros, eficaces y baratos de desarrollo software dirigidos espec��ficamente a esta clase de sistemas es m��s necesario que nunca. A diferencia de lo que ocurr��a hasta hace poco, en la actualidad los avances tecnol��gicos en el campo de los microprocesadores de los ��ltimos tiempos permiten el desarrollo de equipos con prestaciones m��s que suficientes para ejecutar varios sistemas software en una ��nica m��quina. Adem��s, hay sistemas empotrados con requisitos de seguridad (safety) de cuyo correcto funcionamiento depende la vida de muchas personas y/o grandes inversiones econ��micas. Estos sistemas software se dise��an e implementan de acuerdo con unos est��ndares de desarrollo software muy estrictos y exigentes. En algunos casos puede ser necesaria tambi��n la certificaci��n del software. Para estos casos, los sistemas con criticidades mixtas pueden ser una alternativa muy valiosa. En esta clase de sistemas, aplicaciones con diferentes niveles de criticidad se ejecutan en el mismo computador. Sin embargo, a menudo es necesario certificar el sistema entero con el nivel de criticidad de la aplicaci��n m��s cr��tica, lo que hace que los costes se disparen. La virtualizaci��n se ha postulado como una tecnolog��a muy interesante para contener esos costes. Esta tecnolog��a permite que un conjunto de m��quinas virtuales o particiones ejecuten las aplicaciones con unos niveles de aislamiento tanto temporal como espacial muy altos. Esto, a su vez, permite que cada partici��n pueda ser certificada independientemente. Para el desarrollo de sistemas particionados con criticidades mixtas se necesita actualizar los modelos de desarrollo software tradicionales, pues estos no cubren ni las nuevas actividades ni los nuevos roles que se requieren en el desarrollo de estos sistemas. Por ejemplo, el integrador del sistema debe definir las particiones o el desarrollador de aplicaciones debe tener en cuenta las caracter��sticas de la partici��n donde su aplicaci��n va a ejecutar. Tradicionalmente, en el desarrollo de sistemas empotrados, el modelo en V ha tenido una especial relevancia. Por ello, este modelo ha sido adaptado para tener en cuenta escenarios tales como el desarrollo en paralelo de aplicaciones o la incorporaci��n de una nueva partici��n a un sistema ya existente. El objetivo de esta tesis doctoral es mejorar la tecnolog��a actual de desarrollo de sistemas particionados con criticidades mixtas. Para ello, se ha dise��ado e implementado un entorno dirigido espec��ficamente a facilitar y mejorar los procesos de desarrollo de esta clase de sistemas. En concreto, se ha creado un algoritmo que genera el particionado del sistema autom��ticamente. En el entorno de desarrollo propuesto, se han integrado todas las actividades necesarias para desarrollo de un sistema particionado, incluidos los nuevos roles y actividades mencionados anteriormente. Adem��s, el dise��o del entorno de desarrollo se ha basado en la ingenier��a guiada por modelos (Model-Driven Engineering), la cual promueve el uso de los modelos como elementos fundamentales en el proceso de desarrollo. As�� pues, se proporcionan las herramientas necesarias para modelar y particionar el sistema, as�� como para validar los resultados y generar los artefactos necesarios para el compilado, construcci��n y despliegue del mismo. Adem��s, en el dise��o del entorno de desarrollo, la extensi��n e integraci��n del mismo con herramientas de validaci��n ha sido un factor clave. En concreto, se pueden incorporar al entorno de desarrollo nuevos requisitos no-funcionales, la generaci��n de nuevos artefactos tales como documentaci��n o diferentes lenguajes de programaci��n, etc. Una parte clave del entorno de desarrollo es el algoritmo de particionado. Este algoritmo se ha dise��ado para ser independiente de los requisitos de las aplicaciones as�� como para permitir al integrador del sistema implementar nuevos requisitos del sistema. Para lograr esta independencia, se han definido las restricciones al particionado. El algoritmo garantiza que dichas restricciones se cumplir��n en el sistema particionado que resulte de su ejecuci��n. Las restricciones al particionado se han dise��ado con una capacidad expresiva suficiente para que, con un peque��o grupo de ellas, se puedan expresar la mayor parte de los requisitos no-funcionales m��s comunes. Las restricciones pueden ser definidas manualmente por el integrador del sistema o bien pueden ser generadas autom��ticamente por una herramienta a partir de los requisitos funcionales y no-funcionales de una aplicaci��n. El algoritmo de particionado toma como entradas los modelos y las restricciones al particionado del sistema. Tras la ejecuci��n y como resultado, se genera un modelo de despliegue en el que se definen las particiones que son necesarias para el particionado del sistema. A su vez, cada partici��n define qu�� aplicaciones deben ejecutar en ella as�� como los recursos que necesita la partici��n para ejecutar correctamente. El problema del particionado y las restricciones al particionado se modelan matem��ticamente a trav��s de grafos coloreados. En dichos grafos, un coloreado propio de los v��rtices representa un particionado del sistema correcto. El algoritmo se ha dise��ado tambi��n para que, si es necesario, sea posible obtener particionados alternativos al inicialmente propuesto. El entorno de desarrollo, incluyendo el algoritmo de particionado, se ha probado con ��xito en dos casos de uso industriales: el sat��lite UPMSat-2 y un demostrador del sistema de control de una turbina e��lica. Adem��s, el algoritmo se ha validado mediante la ejecuci��n de numerosos escenarios sint��ticos, incluyendo algunos muy complejos, de m��s de 500 aplicaciones. ABSTRACT The importance of embedded software is growing as it is required for a large number of systems. Devising cheap, efficient and reliable development processes for embedded systems is thus a notable challenge nowadays. Computer processing power is continuously increasing, and as a result, it is currently possible to integrate complex systems in a single processor, which was not feasible a few years ago.Embedded systems may have safety critical requirements. Its failure may result in personal or substantial economical loss. The development of these systems requires stringent development processes that are usually defined by suitable standards. In some cases their certification is also necessary. This scenario fosters the use of mixed-criticality systems in which applications of different criticality levels must coexist in a single system. In these cases, it is usually necessary to certify the whole system, including non-critical applications, which is costly. Virtualization emerges as an enabling technology used for dealing with this problem. The system is structured as a set of partitions, or virtual machines, that can be executed with temporal and spatial isolation. In this way, applications can be developed and certified independently. The development of MCPS (Mixed-Criticality Partitioned Systems) requires additional roles and activities that traditional systems do not require. The system integrator has to define system partitions. Application development has to consider the characteristics of the partition to which it is allocated. In addition, traditional software process models have to be adapted to this scenario. The V-model is commonly used in embedded systems development. It can be adapted to the development of MCPS by enabling the parallel development of applications or adding an additional partition to an existing system. The objective of this PhD is to improve the available technology for MCPS development by providing a framework tailored to the development of this type of system and by defining a flexible and efficient algorithm for automatically generating system partitionings. The goal of the framework is to integrate all the activities required for developing MCPS and to support the different roles involved in this process. The framework is based on MDE (Model-Driven Engineering), which emphasizes the use of models in the development process. The framework provides basic means for modeling the system, generating system partitions, validating the system and generating final artifacts. The framework has been designed to facilitate its extension and the integration of external validation tools. In particular, it can be extended by adding support for additional non-functional requirements and support for final artifacts, such as new programming languages or additional documentation. The framework includes a novel partitioning algorithm. It has been designed to be independent of the types of applications requirements and also to enable the system integrator to tailor the partitioning to the specific requirements of a system. This independence is achieved by defining partitioning constraints that must be met by the resulting partitioning. They have sufficient expressive capacity to state the most common constraints and can be defined manually by the system integrator or generated automatically based on functional and non-functional requirements of the applications. The partitioning algorithm uses system models and partitioning constraints as its inputs. It generates a deployment model that is composed by a set of partitions. Each partition is in turn composed of a set of allocated applications and assigned resources. The partitioning problem, including applications and constraints, is modeled as a colored graph. A valid partitioning is a proper vertex coloring. A specially designed algorithm generates this coloring and is able to provide alternative partitions if required. The framework, including the partitioning algorithm, has been successfully used in the development of two industrial use cases: the UPMSat-2 satellite and the control system of a wind-power turbine. The partitioning algorithm has been successfully validated by using a large number of synthetic loads, including complex scenarios with more that 500 applications.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento espec��ficos que realizan una tarea fija durante toda su vida ��til. Para cumplir con requisitos estrictos de coste, tama��o y peso, el equipo de dise��o debe optimizar su funcionamiento para condiciones muy espec��ficas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento m��s inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operaci��n cada vez m��s din��micos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo dise��o tales como: cambios en las caracter��sticas de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de c��mputo, por ejemplo debido a fallos o defectos de fabricaci��n; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema din��micos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptaci��n aut��noma sin intervenci��n humana a lo largo de la vida ��til, permitiendo que tomen sus propias decisiones en tiempo de ejecuci��n. ��stos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras caracter��sticas, las de auto-configuraci��n, auto-optimizaci��n y auto-reparaci��n. T��picamente, la parte soft de un sistema es mayoritariamente la ��nica utilizada para proporcionar algunas capacidades de adaptaci��n a un sistema. Sin embargo, la proporci��n rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones est�� siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia tambi��n aumente. Adem��s, la mejora en metodolog��as de dise��o no ha sido acorde como para poder utilizar toda la capacidad de c��mputo disponible proporcionada por los n��cleos. Por todo ello, no se est��n satisfaciendo adecuadamente las demandas de c��mputo que imponen las nuevas aplicaciones. La soluci��n tradicional para mejorar la proporci��n rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producci��n en masa y adem��s la naturaleza est��tica de su estructura complica la soluci��n a las necesidades de adaptaci��n. Los avances en tecnolog��as de fabricaci��n han hecho que la FPGA, una vez lenta y peque��a, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de c��mputo reconfigurable de gran potencia, con una cantidad enorme de recursos l��gicos computacionales y cores hardware empotrados de procesamiento de se��al y de prop��sito general. Sus capacidades de reconfiguraci��n han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado m��s como est��tico. El motivo es que como en el caso de las FPGAs basadas en tecnolog��a SRAM, la reconfiguraci��n parcial din��mica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecuci��n mientras el resto permanecen activos. Adem��s, este proceso de reconfiguraci��n puede ser ejecutado internamente por el propio dispositivo. El avance tecnol��gico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computaci��n Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicaci��n m��s ex��ticos y menos convencionales que ha posibilitado la computaci��n reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a trav��s de reconfiguraci��n en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biol��gicas naturales, que gu��a la direcci��n del cambio. Es una aplicaci��n m��s del campo de la Computaci��n Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimizaci��n global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resoluci��n de problemas. En analog��a al proceso biol��gico de la evoluci��n, en el hardware evolutivo el sujeto de la evoluci��n es una poblaci��n de circuitos que intenta adaptarse a su entorno mediante una adecuaci��n progresiva generaci��n tras generaci��n. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuaci��n (o fitness) despu��s de ser evaluados, y us��ndolos como padres de la siguiente generaci��n, el algoritmo evolutivo crea una nueva poblaci��n hija usando operadores gen��ticos como la mutaci��n y la recombinaci��n. Seg��n se van sucediendo generaciones, se espera que la poblaci��n en conjunto se aproxime a la soluci��n ��ptima al problema de encontrar una configuraci��n del circuito adecuada que satisfaga las especificaciones. El estado de la tecnolog��a de reconfiguraci��n despu��s de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obst��culo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos p��blicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguraci��n lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los a��os 2000 permiti�� mantener la investigaci��n en el campo mientras la tecnolog��a de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que act��a como un circuito reconfigurable de aplicaci��n espec��fica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguraci��n y aumenta su velocidad (comparada con la reconfiguraci��n nativa). Es un array de nodos computacionales especificados usando descripciones HDL est��ndar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a trav��s de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande act��a como memoria de configuraci��n, por lo que la reconfiguraci��n del VRC es muy r��pida ya que tan s��lo implica la escritura de este registro, el cual controla las se��ales de selecci��n del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de ��rea debido a la implementaci��n simult��nea de cada funci��n en cada nodo del array m��s los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento m��xima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigaci��n sobre sistemas auto-adaptativos. Combinar un sustrato de c��mputo auto-reconfigurable capaz de ser modificado din��micamente en tiempo de ejecuci��n con un algoritmo empotrado que proporcione una direcci��n de cambio, puede ayudar a satisfacer los requisitos de adaptaci��n aut��noma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis est�� por tanto dirigida a contribuir a la auto-adaptaci��n del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de par��metros soft. De esta distinci��n, se derivan dos lineas de trabajo. Por un lado, auto-adaptaci��n param��trica, y por otro auto-adaptaci��n estructural. El objetivo perseguido en el caso de la auto-adaptaci��n param��trica es la implementaci��n de t��cnicas de optimizaci��n evolutiva complejas en sistemas empotrados con recursos limitados para la adaptaci��n param��trica online de circuitos de procesamiento de se��al. La aplicaci��n seleccionada como prueba de concepto es la optimizaci��n para tipos muy espec��ficos de im��genes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresi��n de im��genes. Por tanto, el objetivo requerido de la evoluci��n es una compresi��n adaptativa y m��s eficiente comparada con los procedimientos est��ndar. El principal reto radica en reducir la necesidad de recursos de supercomputaci��n para el proceso de optimizaci��n propuesto en trabajos previos, de modo que se adec��e para la ejecuci��n en sistemas empotrados. En cuanto a la auto-adaptaci��n estructural, el objetivo de la tesis es la implementaci��n de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguraci��n nativas. En este caso, la prueba de concepto es la evoluci��n de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detecci��n de bordes en la imagen. En general, el objetivo es la evoluci��n en tiempo de ejecuci��n de tareas de procesamiento de imagen desconocidas en tiempo de dise��o (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporaci��n de DPR en EHW para evolucionar la arquitectura de un array sist��lico adaptable mediante reconfiguraci��n cuya capacidad de evoluci��n no hab��a sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptaci��n (AE, Adaptation Engine), un motor de reconfiguraci��n (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptaci��n param��trica, la plataforma propuesta est�� caracterizada por: ��� un CE caracterizado por un n��cleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet ��� un algoritmo evolutivo como AE que busca filtros wavelet candidatos a trav��s de un proceso de optimizaci��n param��trica desarrollado espec��ficamente para sistemas caracterizados por recursos de procesamiento limitados ��� un nuevo operador de mutaci��n simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluaci��n r��pida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la b��squeda evolutiva asociada a la adaptaci��n de wavelets. En el caso de adaptaci��n estructural, la plataforma propuesta toma la forma de: ��� un CE basado en una plantilla de array sist��lico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables ��� un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecuci��n ��� un RE hardware que explota la capacidad de reconfiguraci��n nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecuci��n ��� una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posici��n, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: ��� Una plataforma evolutiva basada en FPGA para la auto-adaptaci��n param��trica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptaci��n (AE) evolutivo y un motor de reconfiguraci��n (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptaci��n param��trica y estructural. ��� En cuanto a la auto-adaptaci��n param��trica, las contribuciones principales son: ��� Un motor computacional adaptable mediante registros que permite la adaptaci��n param��trica de los coeficientes de una implementaci��n hardware adaptativa de un n��cleo de DWT. ��� Un motor de adaptaci��n basado en un algoritmo evolutivo desarrollado espec��ficamente para optimizaci��n num��rica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. ��� Un n��cleo IP de DWT auto-adaptativo en tiempo de ejecuci��n para sistemas empotrados que permite la optimizaci��n online del rendimiento de la transformada para compresi��n de im��genes en entornos espec��ficos de despliegue, caracterizados por tipos diferentes de se��al de entrada. ��� Un modelo software y una implementaci��n hardware de una herramienta para la construcci��n evolutiva autom��tica de transformadas wavelet espec��ficas. ��� Por ��ltimo, en cuanto a la auto-adaptaci��n estructural, las contribuciones principales son: ��� Un motor computacional adaptable mediante reconfiguraci��n nativa de FPGAs caracterizado por una plantilla de array sist��lico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de c��mputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. ��� Definici��n de una biblioteca de elementos de procesamiento apropiada para la s��ntesis aut��noma en tiempo de ejecuci��n de diferentes tareas de procesamiento de imagen. ��� Incorporaci��n eficiente de la reconfiguraci��n parcial din��mica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo tambi��n se comparan originalmente los detalles de implementaci��n de ambas propuestas. ��� Una plataforma tolerante a fallos, auto-curativa, que permite la recuperaci��n funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguraci��n, se hace un an��lisis sistem��tico de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. ��� Una plataforma con calidad de filtrado din��mica que permite la adaptaci��n online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, tambi��n se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes din��micamente. Este documento est�� organizado en cuatro partes y nueve cap��tulos. La primera parte contiene el cap��tulo 1, una introducci��n y motivaci��n sobre este trabajo de tesis. A continuaci��n, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el cap��tulo 2 contiene una introducci��n a los conceptos de auto-adaptaci��n y computaci��n auton��mica (autonomic computing) como un campo de investigaci��n m��s general que el muy espec��fico de este trabajo; el cap��tulo 3 introduce la computaci��n evolutiva como la t��cnica para dirigir la adaptaci��n; el cap��tulo 4 analiza las plataformas de computaci��n reconfigurables como la tecnolog��a para albergar hardware auto-adaptativo; y finalmente, el cap��tulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el cap��tulo 6 contiene una declaraci��n de los objetivos de la tesis y la descripci��n de la propuesta en su conjunto, los cap��tulos 7 y 8 abordan la auto-adaptaci��n param��trica y estructural, respectivamente. Finalmente, el cap��tulo 9 de la parte 4 concluye el trabajo y describe caminos de investigaci��n futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: ��� a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients ��� an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources ��� a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: ��� a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes ��� an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library ��� a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time ��� a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. ��� An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. ��� Regarding parametric self-adaptation, main contributions are: ��� A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. ��� An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. ��� A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. ��� A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. ��� Lastly, regarding structural self-adaptation, main contributions are: ��� A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. ��� Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. ��� Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. ��� A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. ��� A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

An application of fuzzy logic for hardware/software partitioning in embedded systems

Hardware/Software partitioning (HSP) is a key task for embedded system co-design. The main goal of this task is to decide which components of an application are to be executed in a general purpose processor (software) and which ones, on a specific hardware, taking into account a set of restrictions expressed by metrics. In last years, several approaches have been proposed for solving the HSP problem, directed by metaheuristic algorithms. However, due to diversity of models and metrics used, the choice of the best suited algorithm is an open problem yet. This article presents the results of applying a fuzzy approach to the HSP problem. This approach is more flexible than many others due to the fact that it is possible to accept quite good solutions or to reject other ones which do not seem good. In this work we compare six metaheuristic algorithms: Random Search, Tabu Search, Simulated Annealing, Hill Climbing, Genetic Algorithm and Evolutionary Strategy. The presented model is aimed to simultaneously minimize the hardware area and the execution time. The obtained results show that Restart Hill Climbing is the best performing algorithm in most cases.

Selective SWIFT-R. A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems

Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.

Fault tolerant embedded systems design by multi-objective optimization

The design of fault tolerant systems is gaining importance in large domains of embedded applications where design constrains are as important as reliability. New software techniques, based on selective application of redundancy, have shown remarkable fault coverage with reduced costs and overheads. However, the large number of different solutions provided by these techniques, and the costly process to assess their reliability, make the design space exploration a very difficult and time-consuming task. This paper proposes the integration of a multi-objective optimization tool with a software hardening environment to perform an automatic design space exploration in the search for the best trade-offs between reliability, cost, and performance. The first tool is commanded by a genetic algorithm which can simultaneously fulfill many design goals thanks to the use of the NSGA-II multi-objective algorithm. The second is a compiler-based infrastructure that automatically produces selective protected (hardened) versions of the software and generates accurate overhead reports and fault coverage estimations. The advantages of our proposal are illustrated by means of a complex and detailed case study involving a typical embedded application, the AES (Advanced Encryption Standard).

Flexible Framework for Real-Time Embedded Systems Based on Mobile Cloud Computing Paradigm

The development of applications as well as the services for mobile systems faces a varied range of devices with very heterogeneous capabilities whose response times are difficult to predict. The research described in this work aims to respond to this issue by developing a computational model that formalizes the problem and that defines adjusting computing methods. The described proposal combines imprecise computing strategies with cloud computing paradigms in order to provide flexible implementation frameworks for embedded or mobile devices. As a result, the imprecise computation scheduling method on the workload of the embedded system is the solution to move computing to the cloud according to the priority and response time of the tasks to be executed and hereby be able to meet productivity and quality of desired services. A technique to estimate network delays and to schedule more accurately tasks is illustrated in this paper. An application example in which this technique is experimented in running contexts with heterogeneous work loading for checking the validity of the proposed model is described.

Flexible processing architecture for maintaining QoS in embedded systems applications

Comunicaci��n presentada en las V Jornadas de Computaci��n Empotrada, Valladolid, 17-19 Septiembre 2014

Supporting the Model-Driven Development of Real-time Embedded Systems with Run-Time Monitoring and Animation via Highly Customizable Code Generation

This paper presents a vision that allows the combined use of model-driven engineering, run-time monitoring, and animation for the development and analysis of components in real-time embedded systems. Key building block in the tool environment supporting this vision is a highly-customizable code generation process. Customization is performed via a configuration specification which describes the ways in which input is provided to the component, the ways in which run-time execution information can be observed, and how these observations drive animation tools. The environment is envisioned to be suitable for different activities ranging from quality assurance to supporting certification, teaching, and outreach and will be built exclusively with open source tools to increase impact. A preliminary prototype implementation is described.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is ���power estimation���. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.

Embedded systems and advanced signal processing for Acousto- Ultrasonic Inspections

Non Destructive Testing (NDT) and Structural Health Monitoring (SHM) are becoming essential in many application contexts, e.g. civil, industrial, aerospace etc., to reduce structures maintenance costs and improve safety. Conventional inspection methods typically exploit bulky and expensive instruments and rely on highly demanding signal processing techniques. The pressing need to overcome these limitations is the common thread that guided the work presented in this Thesis. In the first part, a scalable, low-cost and multi-sensors smart sensor network is introduced. The capability of this technology to carry out accurate modal analysis on structures undergoing flexural vibrations has been validated by means of two experimental campaigns. Then, the suitability of low-cost piezoelectric disks in modal analysis has been demonstrated. To enable the use of this kind of sensing technology in such non conventional applications, ad hoc data merging algorithms have been developed. In the second part, instead, imaging algorithms for Lamb waves inspection (namely DMAS and DS-DMAS) have been implemented and validated. Results show that DMAS outperforms the canonical Delay and Sum (DAS) approach in terms of image resolution and contrast. Similarly, DS-DMAS can achieve better results than both DMAS and DAS by suppressing artefacts and noise. To exploit the full potential of these procedures, accurate group velocity estimations are required. Thus, novel wavefield analysis tools that can address the estimation of the dispersion curves from SLDV acquisitions have been investigated. An image segmentation technique (called DRLSE) was exploited in the k-space to draw out the wavenumber profile. The DRLSE method was compared with compressive sensing methods to extract the group and phase velocity information. The validation, performed on three different carbon fibre plates, showed that the proposed solutions can accurately determine the wavenumber and velocities in polar coordinates at multiple excitation frequencies.

Hardware-software design of embedded systems for intelligent sensing applications

This Thesis wants to highlight the importance of ad-hoc designed and developed embedded systems in the implementation of intelligent sensor networks. As evidence four areas of application are presented: Precision Agriculture, Bioengineering, Automotive and Structural Health Monitoring. For each field is reported one, or more, smart device design and developing, in addition to on-board elaborations, experimental validation and in field tests. In particular, it is presented the design and development of a fruit meter. In the bioengineering field, three different projects are reported, detailing the architectures implemented and the validation tests conducted. Two prototype realizations of an inner temperature measurement system in electric motors for an automotive application are then discussed. Lastly, the HW/SW design of a Smart Sensor Network is analyzed: the network features on-board data management and processing, integration in an IoT toolchain, Wireless Sensor Network developments and an AI framework for vibration-based structural assessment.

Addressing challenges in heterogeneous embedded systems programming: security and performance

Embedded systems are increasingly integral to daily life, improving and facilitating the efficiency of modern Cyber-Physical Systems which provide access to sensor data, and actuators. As modern architectures become increasingly complex and heterogeneous, their optimization becomes a challenging task. Additionally, ensuring platform security is important to avoid harm to individuals and assets. This study primarily addresses challenges in contemporary Embedded Systems, focusing on platform optimization and security enforcement. The initial section of this study delves into the application of machine learning methods to efficiently determine the optimal number of cores for a parallel RISC-V cluster to minimize energy consumption using static source code analysis. Results demonstrate that automated platform configuration is not only viable but also that there is a moderate performance trade-off when relying solely on static features. The second part focuses on addressing the problem of heterogeneous device mapping, which involves assigning tasks to the most suitable computational device in a heterogeneous platform for optimal runtime. The contribution of this section lies in the introduction of novel pre-processing techniques, along with a training framework called Siamese Networks, that enhances the classification performance of DeepLLVM, an advanced approach for task mapping. Importantly, these proposed approaches are independent from the specific deep-learning model used. Finally, this research work focuses on addressing issues concerning the binary exploitation of software running in modern Embedded Systems. It proposes an architecture to implement Control-Flow Integrity in embedded platforms with a Root-of-Trust, aiming to enhance security guarantees with limited hardware modifications. The approach involves enhancing the architecture of a modern RISC-V platform for autonomous vehicles by implementing a side-channel communication mechanism that relays control-flow changes executed by the process running on the host core to the Root-of-Trust. This approach has limited impact on performance and it is effective in enhancing the security of embedded platforms.

Using a prioritized MAC protocol to execute the database operation join in networked embedded computer systems

Database query languages on relations (for example SQL) make it possible to join two relations. This operation is very common in desktop/server database systems but unfortunately query processing systems in networked embedded computer systems currently do not support this operation; specifically, the query processing systems TAG, TinyDB, Cougar do not support this. We show how a prioritized medium access control (MAC) protocol can be used to efficiently execute the database operation join for networked embedded computer systems where all computer nodes are in a single broadcast domain.