859 resultados para Delay of Gratification
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A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.
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We consider a discrete time system with packets arriving randomly at rate lambda per slot to a fading point-to-point link, for which the transmitter can control the number of packets served in a slot by varying the transmit power. We provide an asymptotic characterization of the minimum average delay of the packets, when average transmitter power is a small positive quantity V more than the minimum average power required for queue stability. We show that the minimum average delay will grow either as log (1/V) or 1/V when V down arrow 0, for certain sets of values of lambda. These sets are determined by the distribution of fading gain, the maximum number of packets which can be transmitted in a slot, and the assumed transmit power function, as a function of the fading gain and the number of packets transmitted. We identify a case where the above behaviour of the tradeoff differs from that obtained from a previously considered model, in which the random queue length process is assumed to evolve on the non-negative real line.
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The optimal power-delay tradeoff is studied for a time-slotted independently and identically distributed fading point-to-point link, with perfect channel state information at both transmitter and receiver, and with random packet arrivals to the transmitter queue. It is assumed that the transmitter can control the number of packets served by controlling the transmit power in the slot. The optimal tradeoff between average power and average delay is analyzed for stationary and monotone transmitter policies. For such policies, an asymptotic lower bound on the minimum average delay of the packets is obtained, when average transmitter power approaches the minimum average power required for transmitter queue stability. The asymptotic lower bound on the minimum average delay is obtained from geometric upper bounds on the stationary distribution of the queue length. This approach, which uses geometric upper bounds, also leads to an intuitive explanation of the asymptotic behavior of average delay. The asymptotic lower bounds, along with previously known asymptotic upper bounds, are used to identify three new cases where the order of the asymptotic behavior differs from that obtained from a previously considered approximate model, in which the transmit power is a strictly convex function of real valued service batch size for every fade state.
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For a sphere electrode enclosed in finite-volume electrolyte, the measured current will deviate from the result predicted by the semi-infinite diffusion theory after some time. By random-walk simulation, we compared this time to the one needed for diffusion layer to reach electrolyte boundary, and revealed a clear signal delay of electrochemical current. Further we presented a quantitative description of this delay time. The simulation results suggested that the semi-infinite diffusion theory can even be applied when the theoretical diffusion layer grows to 1.28 electrolyte thicknesses, with an accuracy better than 0.5%. We attributed this time delay to the molecules' finite propagation velocity. Finally, we discussed how this delay can influence and facilitate the following electrochemical detection towards the nanometer and single-cell scale.
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With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.
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The R-matrix incorporating time (RMT) method is a method developed recently for solving the time-dependent Schrödinger equation for multielectron atomic systems exposed to intense short-pulse laser light. We have employed the RMT method to investigate the time delay in the photoemission of an electron liberated from a 2p orbital in a neon atom with respect to one released from a 2s orbital following absorption of an attosecond xuv pulse. Time delays due to xuv pulses in the range 76-105 eV are presented. For an xuv pulse at the experimentally relevant energy of 105.2 eV, we calculate the time delay to be 10.2±1.3 attoseconds (as), somewhat larger than estimated by other theoretical calculations, but still a factor of 2 smaller than experiment. We repeated the calculation for a photon energy of 89.8 eV with a larger basis set capable of modeling correlated-electron dynamics within the neon atom and the residual Ne ion. A time delay of 14.5±1.5 as was observed, compared to a 16.7±1.5 as result using a single-configuration representation of the residual Ne+ ion.
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Most adaptive linearization circuits for the nonlinear amplifier have a feedback loop that returns the output signal oj'tne eunplifier to the lineurizer. The loop delay of the linearizer most be controlled precisely so that the convergence of the linearizer should be assured lot this Letter a delay control circuit is presented. It is a delay lock loop (ULL) with it modified early-lute gate and can he easily applied to a DSP implementation. The proposed DLL circuit is applied to an adaptive linearizer with the use of a polynomial predistorter, and the simulalion for a 16-QAM signal is performed. The simulation results show that the proposed DLL eliminates the delay between the reference input signal and the delayed feedback signal of the linearizing circuit perfectly, so that the predistorter polynomial coefficients converge into the optimum value and a high degree of linearization is achieved
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Esta tesis presenta un novedoso marco de referencia para el análisis y optimización del retardo de codificación y descodificación para vídeo multivista. El objetivo de este marco de referencia es proporcionar una metodología sistemática para el análisis del retardo en codificadores y descodificadores multivista y herramientas útiles en el diseño de codificadores/descodificadores para aplicaciones con requisitos de bajo retardo. El marco de referencia propuesto caracteriza primero los elementos que tienen influencia en el comportamiento del retardo: i) la estructura de predicción multivista, ii) el modelo hardware del codificador/descodificador y iii) los tiempos de proceso de cuadro. En segundo lugar, proporciona algoritmos para el cálculo del retardo de codificación/ descodificación de cualquier estructura arbitraria de predicción multivista. El núcleo de este marco de referencia consiste en una metodología para el análisis del retardo de codificación/descodificación multivista que es independiente de la arquitectura hardware del codificador/descodificador, completada con un conjunto de modelos que particularizan este análisis del retardo con las características de la arquitectura hardware del codificador/descodificador. Entre estos modelos, aquellos basados en teoría de grafos adquieren especial relevancia debido a su capacidad de desacoplar la influencia de los diferentes elementos en el comportamiento del retardo en el codificador/ descodificador, mediante una abstracción de su capacidad de proceso. Para revelar las posibles aplicaciones de este marco de referencia, esta tesis presenta algunos ejemplos de su utilización en problemas de diseño que afectan a codificadores y descodificadores multivista. Este escenario de aplicación cubre los siguientes casos: estrategias para el diseño de estructuras de predicción que tengan en consideración requisitos de retardo además del comportamiento tasa-distorsión; diseño del número de procesadores y análisis de los requisitos de velocidad de proceso en codificadores/ descodificadores multivista dado un retardo objetivo; y el análisis comparativo del comportamiento del retardo en codificadores multivista con diferentes capacidades de proceso e implementaciones hardware. ABSTRACT This thesis presents a novel framework for the analysis and optimization of the encoding and decoding delay for multiview video. The objective of this framework is to provide a systematic methodology for the analysis of the delay in multiview encoders and decoders and useful tools in the design of multiview encoders/decoders for applications with low delay requirements. The proposed framework characterizes firstly the elements that have an influence in the delay performance: i) the multiview prediction structure ii) the hardware model of the encoder/decoder and iii) frame processing times. Secondly, it provides algorithms for the computation of the encoding/decoding delay of any arbitrary multiview prediction structure. The core of this framework consists in a methodology for the analysis of the multiview encoding/decoding delay that is independent of the hardware architecture of the encoder/decoder, which is completed with a set of models that particularize this delay analysis with the characteristics of the hardware architecture of the encoder/decoder. Among these models, the ones based in graph theory acquire special relevance due to their capacity to detach the influence of the different elements in the delay performance of the encoder/decoder, by means of an abstraction of its processing capacity. To reveal possible applications of this framework, this thesis presents some examples of its utilization in design problems that affect multiview encoders and decoders. This application scenario covers the following cases: strategies for the design of prediction structures that take into consideration delay requirements in addition to the rate-distortion performance; design of number of processors and analysis of processor speed requirements in multiview encoders/decoders given a target delay; and comparative analysis of the encoding delay performance of multiview encoders with different processing capabilities and hardware implementations.
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In this paper, we propose a novel control scheme for bilateral teleoperation of n degree-of-freedom (DOF) nonlinear robotic systems with time-varying communication delay. We consider that the human operator contains a constant force on the local manipulator. The local and remote manipulators are coupled using state convergence control scheme. By choosing a Lyapunov-Krasovskii functional, we show that the local-remote teleoperation system is asymptotically stable. It is also shown that, in the case of reliable communication protocols, the proposed scheme guarantees that the remote manipulator tracks the delayed trajectory of the local manipulator. The time delay of communication channel is assumed to be unknown and randomly time varying, but the upper bounds of the delay interval and the derivative of the delay are assumed to be known.
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We propose a novel control scheme for bilateral teleoperation of n degree-of-freedom (DOF) nonlinear robotic systems with time-varying communication delay. A major contribution from this work lies in the demonstration that the structure of a state convergence algorithm can be also applied to nth-order nonlinear teleoperation systems. By choosing a Lyapunov Krasovskii functional, we show that the local-remote teleoperation system is asymptotically stable. The time delay of communication channel is assumed to be unknown and randomly time varying, but the upper bounds of the delay interval and the derivative of the delay are assumed to be known.
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Thesis (Master's)--University of Washington, 2016-06
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Pulse oximetry is commonly used as an arterial blood oxygen saturation (SaO(2)) measure. However, its other serial output, the photoplethysmography (PPG) signal, is not as well studied. Raw PPG signals can be used to estimate cardiovascular measures like pulse transit time (PTT) and possibly heart rate (HR). These timing-related measurements are heavily dependent on the minimal variability in phase delay of the PPG signals. Masimo SET (R) Rad-9 (TM) and Novametrix Oxypleth oximeters were investigated for their PPG phase characteristics on nine healthy adults. To facilitate comparison, PPG signals were acquired from fingers on the same hand in a random fashion. Results showed that mean PTT variations acquired from the Masimo oximeter (37.89 ms) were much greater than the Novametrix (5.66 ms). Documented evidence suggests that I ms variation in PTT is equivalent to I mmHg change in blood pressure. Moreover, the PTT trend derived from the Masimo oximeter can be mistaken as obstructive sleep apnoeas based on the known criteria. HR comparison was evaluated against estimates attained from an electrocardiogram (ECG). Novametrix differed from ECG by 0.71 +/- 0.58% (p < 0.05) while Masimo differed by 4.51 +/- 3.66% (p > 0.05). Modem oximeters can be attractive for their improved SaO(2) measurement. However, using raw PPG signals obtained directly from these oximeters for timing-related measurements warrants further investigations.
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We have studied the soliton propagation through a segment containing random pointlike scatterers. In the limit of small concentration of scatterers when the mean distance between the scatterers is larger than the soliton width, a method has been developed for obtaining the statistical characteristics of the soliton transmission through the segment. The method is applicable for any classical particle traversing through a disordered segment with the given velocity transformation after each act of scattering. In the case of weak scattering and relatively short disordered segment the transmission time delay of a fast soliton is mostly determined by the shifts of the soliton center after each act of scattering. For sufficiently long segments the main contribution to the delay is due to the shifts of the amplitude and velocity of a fast soliton after each scatterer. Corresponding crossover lengths for both cases of light and heavy solitons have been obtained. We have also calculated the exact probability density function of the soliton transmission time delay for a sufficiently long segment. In the case of weak identical scatterers the latter is a universal function which depends on a sole parameter—the mean number of scatterers in a segment.
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A theoretical and experimental investigation of the time delay characteristics of fiber Bragg grating-based Sagnac loops (FBGSLs) is presented. Analytic expressions for the phase and time delay of the FBGSL have been derived and excellent agreement is found between their predictions and experimental results for configurations incorporating uniform-period and chirped-period gratings. For symmetrical grating structures, it is found that the FBGSL time delay response is similar to that of the incorporated grating; with asymmetrical gratings, the FBGSL response is quite different. It is shown that wavelength-division-multiplexing filters exhibiting near-zero dispersion characteristics can be implemented using FBGSLs.
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This paper presents the preliminary results in establishing a strategy for predicting Zenith Tropospheric Delay (ZTD) and relative ZTD (rZTD) between Continuous Operating Reference Stations (CORS) in near real-time. It is anticipated that the predicted ZTD or rZTD can assist the network-based Real-Time Kinematic (RTK) performance over long inter-station distances, ultimately, enabling a cost effective method of delivering precise positioning services to sparsely populated regional areas, such as Queensland. This research firstly investigates two ZTD solutions: 1) the post-processed IGS ZTD solution and 2) the near Real-Time ZTD solution. The near Real-Time solution is obtained through the GNSS processing software package (Bernese) that has been deployed for this project. The predictability of the near Real-Time Bernese solution is analyzed and compared to the post-processed IGS solution where it acts as the benchmark solution. The predictability analyses were conducted with various prediction time of 15, 30, 45, and 60 minutes to determine the error with respect to timeliness. The predictability of ZTD and relative ZTD is determined (or characterized) by using the previously estimated ZTD as the predicted ZTD of current epoch. This research has shown that both the ZTD and relative ZTD predicted errors are random in nature; the STD grows from a few millimeters to sub-centimeters while the predicted delay interval ranges from 15 to 60 minutes. Additionally, the RZTD predictability shows very little dependency on the length of tested baselines of up to 1000 kilometers. Finally, the comparison of near Real-Time Bernese solution with IGS solution has shown a slight degradation in the prediction accuracy. The less accurate NRT solution has an STD error of 1cm within the delay of 50 minutes. However, some larger errors of up to 10cm are observed.