Multiloop controller and reference generator for a dynamic voltage restorer implementation

This paper deals with the design and analysis of a Dynamic Voltage Restorer output voltage control. Such control is based on a multiloop strategy, with an inner current PID regulator and an outer P+Resonant voltage controller. The inner regulator is applied on the output inductor current. It will be also demonstrated how the load current behavior may influence in the DVR output voltage, which justifies the need for the resonant controller. Additionally, it will be discussed the application of a modified algorithm for the identification of the DVR voltage references, which is based on a previously presented positive sequence detector. Since the studied three-phase DVR is assumed to be based on three identical H-bridge converters, all the analysis and design procedures were realized by means of single-phase equivalent circuits. The discussions and conclusions are supported by theoretical calculations, nonlinear simulations and some experimental results. ©2008 IEEE.

Transistor current -- voltage relationships : a consideration of high voltage dc operation of junction transistors with special reference to avalanche multiplication and related phenomena /

"August 6, 1963"

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitorvoltage tripler architecture with MOSFET capacitors, which results in an, area approximately eight times smaller than using MiM capacitors for the 0.131mu m CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit is self-clocked, using a phase controller designed specifically to work with an amorphous silicon solar cell, in order to obtain themaximum available power from the cell. This will be done by tracking its maximum power point (MPPT) using the fractional open circuit voltage method. Electrical simulations of the circuit, together with an equivalent electrical model of an amorphous silicon solar cell, show that the circuit can deliver apower of 1132 mu W to the load, corresponding to a maximum efficiency of 66.81%.

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

A CMOS variable width short-pulse generator circuit for UWB RADAR applications

IEEE International Symposium on Circuits and Systems, pp. 2713 – 2716, Seattle, EUA

Low power low voltage quadrature RC oscillators for modern RF receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e Tecnologia

CMOS indoor light energy harvesting system for wireless sensing applications

Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores

Design of a CMOS amplifier for breast cancer detection

A transimpedance amplifier (TIA) is used, in radiation detectors like the positron emission tomography(PET), to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a desired amplitude and shape. The TIA must have the lowest noise possible to maximize the output. To achieve a low noise, a circuit topology is proposed where an auxiliary path is added to the feedback TIA input, In this auxiliary path a differential transconductance block is used to transform the node voltage in to a current, this current is then converted to a voltage pulse by a second feedback TIA complementary to the first one, with the same amplitude but 180º out of phase with the first feedback TIA. With this circuit the input signal of the TIA appears differential at the output, this is used to try an reduced the circuit noise. The circuit is tested with two different devices, the Avalanche photodiodes (APD) and the Silicon photomultiplier (SIPMs). From the simulations we find that when using s SIPM with Rx=20kΩ and Cx=50fF the signal to noise ratio is increased from 59 when using only one feedback TIA to 68.3 when we use an auxiliary path in conjunction with the feedback TIA. This values where achieved with a total power consumption of 4.82mv. While the signal to noise ratio in the case of the SIPM is increased with some penalty in power consumption.

A piezoelectric based energy harvester interface for a CMOS wireless sensor IC

In this thesis a piezoelectric energy harvesting system, responsible for regulating the power output of a piezoelectric transducer subjected to ambient vibration, is designed to power an RF receiver with a 6 mW power consump-tion. The electrical characterisation of the chosen piezoelectric transducer is the starting point of the design, which subsequently presents a full-bridge cross-coupled rectifier that rectifies the AC output of the transducer and a low-dropout regulator responsible for delivering a constant voltage system output of 0.6 V, with low voltage ripple, which represents the receiver’s required sup-ply voltage. The circuit is designed using CMOS 130 nm UMC technology, and the system presents an inductorless architecture, with reduced area and cost. The electrical simulations run for the complete circuit lead to the conclusion that the proposed piezoelectric energy harvesting system is a plausible solution to power the RF receiver, provided that the chosen transducer is subjected to moderate levels of vibration.

Readout electronics for low dark count pixel detectors based on geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

The high sensitivity and excellent timing accuracy of Geiger mode avalanche photodiodes makes them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase of the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 µm and a high integration 0.13 µm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

A multisampling time-domain CMOS imager with synchronous readout circuit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Winner-take-all circuit using CMOS technology

In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).