Polyphase Implementation of Non-recursive Comb Decimators for Sigma-Delta A/D Converters

In a sigma-delta analog to digital (A/D) As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs are The first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters.

Pré-regulador retificador boost com controle digital por valores médios, para sistema de iluminação fluorescente multi-lâmpadas, utilizando dispositivo FPGA e VHDL

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Numerical Modelling of Graphene Nanoribbon-fets for Analog and Digital Applications

Graphene, that is a monolayer of carbon atoms arranged in a honeycomb lattice, has been isolated only recently from graphite. This material shows very attractive physical properties, like superior carrier mobility, current carrying capability and thermal conductivity. In consideration of that, graphene has been the object of large investigation as a promising candidate to be used in nanometer-scale devices for electronic applications. In this work, graphene nanoribbons (GNRs), that are narrow strips of graphene, for which a band-gap is induced by the quantum confinement of carriers in the transverse direction, have been studied. As experimental GNR-FETs are still far from being ideal, mainly due to the large width and edge roughness, an accurate description of the physical phenomena occurring in these devices is required to have valuable predictions about the performance of these novel structures. A code has been developed to this purpose and used to investigate the performance of 1 to 15-nm wide GNR-FETs. Due to the importance of an accurate description of the quantum effects in the operation of graphene devices, a full-quantum transport model has been adopted: the electron dynamics has been described by a tight-binding (TB) Hamiltonian model and transport has been solved within the formalism of the non-equilibrium Green's functions (NEGF). Both ballistic and dissipative transport are considered. The inclusion of the electron-phonon interaction has been taken into account in the self-consistent Born approximation. In consideration of their different energy band-gap, narrow GNRs are expected to be suitable for logic applications, while wider ones could be promising candidates as channel material for radio-frequency applications.

The Extremely Red, Young L Dwarf PSO J318.5338-22.8603: a Free-Floating Planetary-Mass Analog to Directly Imaged Young Gas-Giant Planets

We have discovered using Pan-STARRS1 an extremely red late-L dwarf, which has (J - K)(MKO) = 2.78 and (J - K) (2MASS) = 2.84, making it the reddest known field dwarf and second only to 2MASS J1207-39b among substellar companions. Near-IR spectroscopy shows a spectral type of L7 +/- 1 and reveals a triangular H-band continuum and weak alkali (K I and Na I) lines, hallmarks of low surface gravity. Near-IR astrometry from the Hawaii Infrared Parallax Program gives a distance of 24.6 +/- 1.4 pc and indicates a much fainter J-band absolute magnitude than field L dwarfs. The position and kinematics of PSO J318.5-22 point to membership in the beta Pic moving group. Evolutionary models give a temperature of 1160(-40)(+30) K and a mass of 6.5(-1.0)(+1.3) M-Jup, making PSO J318.5-22 one of the lowest mass free-floating objects in the solar neighborhood. This object adds to the growing list of low-gravity field L dwarfs and is the first to be strongly deficient in methane relative to its estimated temperature. Comparing their spectra suggests that young L dwarfs with similar ages and temperatures can have different spectral signatures of youth. For the two objects with well constrained ages (PSO J318.5-22 and 2MASS J0355+11), we find their temperatures are approximate to 400 K cooler than field objects of similar spectral type but their luminosities are similar, i.e., these young L dwarfs are very red and unusually cool but not "underluminous." Altogether, PSO J318.5-22 is the first free-floating object with the colors, magnitudes, spectrum, luminosity, and mass that overlap the young dusty planets around HR 8799 and 2MASS J1207-39

Power network in the loop : subsystem testing using a switching amplifier

“Hardware in the Loop” (HIL) testing is widely used in the automotive industry. The sophisticated electronic control units used for vehicle control are usually tested and evaluated using HIL-simulations. The HIL increases the degree of realistic testing of any system. Moreover, it helps in designing the structure and control of the system under test so that it works effectively in the situations that will be encountered in the system. Due to the size and the complexity of interaction within a power network, most research is based on pure simulation. To validate the performance of physical generator or protection system, most testing is constrained to very simple power network. This research, however, examines a method to test power system hardware within a complex virtual environment using the concept of the HIL. The HIL testing for electronic control units and power systems protection device can be easily performed at signal level. But performance of power systems equipments, such as distributed generation systems can not be evaluated at signal level using HIL testing. The HIL testing for power systems equipments is termed here as ‘Power Network in the Loop’ (PNIL). PNIL testing can only be performed at power level and requires a power amplifier that can amplify the simulation signal to the power level. A power network is divided in two parts. One part represents the Power Network Under Test (PNUT) and the other part represents the rest of the complex network. The complex network is simulated in real time simulator (RTS) while the PNUT is connected to the Voltage Source Converter (VSC) based power amplifier. Two way interaction between the simulator and amplifier is performed using analog to digital (A/D) and digital to analog (D/A) converters. The power amplifier amplifies the current or voltage signal of simulator to the power level and establishes the power level interaction between RTS and PNUT. In the first part of this thesis, design and control of a VSC based power amplifier that can amplify a broadband voltage signal is presented. A new Hybrid Discontinuous Control method is proposed for the amplifier. This amplifier can be used for several power systems applications. In the first part of the thesis, use of this amplifier in DSTATCOM and UPS applications are presented. In the later part of this thesis the solution of network in the loop testing with the help of this amplifier is reported. The experimental setup for PNIL testing is built in the laboratory of Queensland University of Technology and the feasibility of PNIL testing has been evaluated using the experimental studies. In the last section of this thesis a universal load with power regenerative capability is designed. This universal load is used to test the DG system using PNIL concepts. This thesis is composed of published/submitted papers that form the chapters in this dissertation. Each paper has been published or submitted during the period of candidature. Chapter 1 integrates all the papers to provide a coherent view of wide bandwidth switching amplifier and its used in different power systems applications specially for the solution of power systems testing using PNIL.

Power management and power flow control with back-to-back converters in a utility connected microgrid

This paper proposes a method for power flow control between utility and microgrid through back-to-back converters, which facilitates desired real and reactive power flow between utility and microgrid. In the proposed control strategy, the system can run in two different modes depending on the power requirement in the microgrid. In mode-1, specified amount of real and reactive power are shared between the utility and the microgrid through the back-to-back converters. Mode-2 is invoked when the power that can be supplied by the DGs in the microgrid reaches its maximum limit. In such a case, the rest of the power demand of the microgrid has to be supplied by the utility. An arrangement between DGs in the microgrid is proposed to achieve load sharing in both grid connected and islanded modes. The back-to-back converters also provide total frequency isolation between the utility and the microgrid. It is shown that the voltage or frequency fluctuation in the utility side has no impact on voltage or power in microgrid side. Proper relay-breaker operation coordination is proposed during fault along with the blocking of the back-to-back converters for seamless resynchronization. Both impedance and motor type loads are considered to verify the system stability. The impact of dc side voltage fluctuation of the DGs and DG tripping on power sharing is also investigated. The efficacy of the proposed control ar-rangement has been validated through simulation for various operating conditions. The model of the microgrid power system is simulated in PSCAD.

Control and protection of a microgrid connected to utility through back-to-back converters

This paper discusses the control and protection of a microgrid that is connected to utility through back-to-back converters. The back-to-back converter connection facilitates bidirectional power flow between the utility and the microgrid. These converters can operate in two different modes–one in which a fixed amount of power is drawn from the utility and the other in which the microgrid power shortfall is supplied by the utility. In the case of a fault in the utility or microgrid side, the protection system should act not only to clear the fault but also to block the back-to-back converters such that its dc bus voltage does not fall during fault. Furthermore, a converter internal mechanism prevents it from supplying high current during a fault and this complicates the operation of a protection system. To overcome this, an admittance based relay scheme is proposed, which has an inverse time characteristic based on measured admittance of the line. The proposed protection and control schemes are able to ensure reliable operation of the microgrid.

Design led innovation : shifting from smart follower to digital strategy leader in the Australian airport sector

This paper presents and discusses organisational barriers and opportunities arising from the dissemination of design led innovation within a leading Australian airport corporation. This research is part of a greater action research program which aims to integrate design as a strategic capability through design led innovation within Australian businesses. Findings reveal that there is an opportunity to employ the theoretical framework and tools of design led innovation in practice to build collaborative idea generation by involving customers and stakeholders within the proposal of new to world propositions. The iterative gathering of deep customer insights also provided an opportunity to leverage a greater understanding of stakeholders and customers in strengthening continuing business partnerships through co-design. Challenges to the design led approach include resistance to the exploratory nature of gathering deep customer insights, the testing of long held assumptions and market data, and the disruption of an organisational mindset geared toward risk aversion instilled within the aviation industry. The implication from these findings is that design led innovation can provide the critical platform to allow for a business to grow and sustain internal design capabilities necessary to challenge prevailing assumptions about how its business model operates to deliver value to customers and stakeholders alike. The platform of design led innovation also provides an avenue to support a cultural transformation towards anticipating future needs necessary for establishing a position of leadership within the broader economic environment.

Teaching digital media to digital natives

The majority of today's undergraduate students are 'digital natives'; a generation born into a world shaped by digital technologies. It is important to understand the significance of this when considering how to teach Digital Media to digital natives. This paper examines the analogies to literacy that recur in digital native debates. It argues that if the concept of digital literacy is to be useful, educators must attend to the multiple layers and proficiencies that comprise literacy. Rather than completely dispose of old teaching methods, updated pedagogical practices should integrate analysis and critique with exploratory and creative modes of learning.

A non-linear analogue-to-digital converter for linearization of transducer input-output relationships

Analogue and digital techniques for linearization of non-linear input-output relationship of transducers are briefly reviewed. The condition required for linearizing a non-linear function y = f(x) using a non-linear analogue-to-digital converter, is explained. A simple technique to construct a non-linear digital-to-analogue converter, based on ' segments of equal digital interval ' is described. The technique was used to build an N-DAC which can be employed in a successive approximation or counter-ramp type ADC to linearize the non-linear transfer function of a thermistor-resistor combination. The possibility of achieving an order of magnitude higher accuracy in the measurement of temperature is shown.

Pipeline Analog To Ternary Converter

The paper describes the application of the pipelining principle to the realization of an analogue-to-ternary converter. The circuit shows a considerable saving in hard-ware compared with an earlier proposed circuit. The main hardware components used are analogue comparators, subtractors and the delay elements; hence this method of A/T conversion can operate at a higher sampling frequency.

A dual-slope analogue-to-digital converter for generating polynomials

A new digital polynomial generator using the principle of dual-slope analogue-to-digital conversion is proposed. Techniques for realizing a wide range of integer as well as fractional coefficients to obtain the desired polynomial have been discussed. The suitability of realizing the proposed polynomial generator in integrated circuit form is also indicated.

An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.