Nanochromics: old materials, new structures and architectures for high performance devices

Due to the development of nanoscience, the interest in electrochromism has increased and new assemblies of electrochromic materials at nanoscale leading to higher efficiencies and chromatic contrasts, low switching times and the possibility of color tuning have been developed. These advantages are reached due to the extensive surface area found in nanomaterials and the large amount of organic electrochromic molecules that can be easily attached onto inorganic nanoparticles, as TiO2 or SiO2. Moreover, the direct contact between electrolyte and nanomaterials produces high ionic transfer rates, leading to fast charge compensation, which is essential for high performance electrochromic electrodes. Recently, the layer-by-layer technique was presented as an interesting way to produce different architectures by the combination of both electrochromic nanoparticles and polymers. The present paper shows some of the newest insights into nanochromic science.

A Specialized Processor for Emulating Peripherals of the PIC Microcontroller

This paper proposes and describes an architecture that allows the both engineer and programmer for defining and quantifying which peripheral of a microcontroller will be important to the particular project. For each application, it is necessary to use different types of peripherals. In this study, we have verified the possibility for emulating the behavior of peripheral in specifically CPUs. These CPUs hold a RAM memory, where code spaces specifically written for them could represent the behavior of some target peripheral, which are loaded and executed on it. We believed that the proposed architecture will provide larger flexibility in the use of the microcontrolles since this ""dedicated hardware components"" don`t execute to a special function, but it is a hardware capable to self adapt to the needs of each project. This research had as fundament a comparative study of four current microcontrollers. Preliminary tests using VHDL and FPGAs were done.

Reducing fuel consumption through modular vehicle architectures

By identifying energy waste streams in vehicles fuel consumption and introducing the concept of lean driving systems, a technological gap for reducing fuel consumption was identified. This paper proposes a solution to overcome this gap, through a modular vehicle architecture aligned with driving patterns. It does not address detailed technological solutions; instead it models the potential effects in fuel consumption through a modular concept of a vehicle and quantifies their dependence on vehicle design parameters (manifesting as the vehicle mass) and user behavior parameters (driving patterns manifesting as the use of a modular car in lighter and heavier mode, in urban and highway cycles). Modularity has been functionally applied in automotive industry as manufacture and assembly management strategies; here it is thought as a product development strategy for flexibility in use, driven by environmental concerns and enabled by social behaviors. The authors argue this concept is a step forward in combining technological solutions and social behavior, of which eco-driving is a vivid example, and potentially evolutionary to a lean, more sustainable, driving culture.

Multilayer Architectures Based on a-SiC:H Material: Tunable Wavelength Filters in Optical Processing Devices

The characteristics of tunable wavelength filters based on a-SiC:H multilayered stacked pin cells are studied both theoretically and experimentally. The optical transducers were produced by PECVD and tested for a proper fine tuning of the cyan and yellow fluorescent proteins emission. The active device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n heterostructures sandwiched between two transparent contacts. Experimental data on spectral response analysis, current-voltage characteristics and color and transmission rate discrimination are reported. Cyan and yellow fluorescent input channels were transmitted together, each one with a specific transmission rate and different intensities. The multiplexed optical signal was analyzed by reading out, under positive and negative applied voltages, the generated photocurrents. Results show that the optimized optical transducer has the capability of combining the transient fluorescent signals onto a single output signal without losing any specificity (color and intensity). It acts as a voltage controlled optical filter: when the applied voltages are chosen appropriately the transducer can select separately the cyan and yellow channel emissions (wavelength and frequency) and also to quantify their relative intensities. A theoretical analysis supported by a numerical simulation is presented.

Optimization, high availability and redundancy in information communications and technology using networks and systems virtualization architectures

Mestrado em Engenharia Informática

Optical processing devices based on a-SiCH multilayer architectures

Red, green and blue optical signals were directed to an a-SiC:H multilayered device, each one with a specific transmission rate. The combined optical signal was analyzed by reading out, under different applied voltages, the generated photocurrent. Results show that when a chromatic time dependent wavelength combination with different transmission rates irradiates the multilayered structure, the device operates as a tunable wavelength filter and can be used in wavelength division multiplexing systems for short range communications. An application to fluorescent proteins detection is presented. (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Multiprocessor platform using LEON3 processor

The recent advances in embedded systems world, lead us to more complex systems with application specific blocks (IP cores), the System on Chip (SoC) devices. A good example of these complex devices can be encountered in the cell phones that can have image processing cores, communication cores, memory card cores, and others. The need of augmenting systems’ processing performance with lowest power, leads to a concept of Multiprocessor System on Chip (MSoC) in which the execution of multiple tasks can be distributed along various processors. This thesis intends to address the creation of a synthesizable multiprocessing system to be placed in a FPGA device, providing a good flexibility to tailor the system to a specific application. To deliver a multiprocessing system, will be used the synthesisable 32-bit SPARC V8 compliant, LEON3 processor.

From task scheduling in single processor environments to message scheduling in a PROFIBUS fieldbus network

In this paper we survey the most relevant results for the prioritybased schedulability analysis of real-time tasks, both for the fixed and dynamic priority assignment schemes. We give emphasis to the worst-case response time analysis in non-preemptive contexts, which is fundamental for the communication schedulability analysis. We define an architecture to support priority-based scheduling of messages at the application process level of a specific fieldbus communication network, the PROFIBUS. The proposed architecture improves the worst-case messages’ response time, overcoming the limitation of the first-come-first-served (FCFS) PROFIBUS queue implementations.

A parallel programming model for ada

Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada.

Hybrid wired/wireless PROFIBUS architectures: performance study based on simulation models

The problem of providing a hybrid wired/wireless communications for factory automation systems is still an open issue, notwithstanding the fact that already there are some solutions. This paper describes the role of simulation tools on the validation and performance analysis of two wireless extensions for the PROFIBUS protocol. In one of them, the Intermediate Systems, which connect wired and wireless network segments, operate as repeaters. In the other one the Intermediate Systems operate as bridge. We also describe how the analytical analysis proposed for these kinds of networks can be used for the setting of some network parameters and for the guaranteeing real-time behaviour of the system. Additionally, we also compare the bridge-based solution simulation results with the analytical results.

Performance comparison of a VDFLL versus VDLL and scalar GNSS receiver architectures in Harsh scenarios

We analyze the advantages and drawbacks of a vector delay/frequency-locked loop (VDFLL) architecture regarding the conventional scalar and the vector delay-locked loop (VDLL) architectures for GNSS receivers in harsh scenarios that include ionospheric scintillation, multipath, and high dynamics motion. The VDFLL is constituted by a bank of code and frequency discriminators feeding a central extended Kaiman filter (EKF) that estimates the receiver's position, velocity, and clock bias. Both code and frequency loops are closed vectorially through the EKF. The VDLL closes the code loop vectorially and the phase loops through individual PLLs while the scalar receiver closes both loops by means of individual independent PLLs and DLLs.

Using the learning tools interoperability framework for LMS integration in service oriented architectures

The LMS plays an indisputable role in the majority of the eLearning environments. This eLearning system type is often used for presenting, solving and grading simple exercises. However, exercises from complex domains, such as computer programming, require heterogeneous systems such as evaluation engines, learning objects repositories and exercise resolution environments. The coordination of networks of such disparate systems is rather complex. This work presents a standard approach for the coordination of a network of eLearning systems supporting the resolution of exercises. The proposed approach use a pivot component embedded in the LMS with two roles: provide an exercise resolution environment and coordinate the communication between the LMS and other systems exposing their functions as web services. The integration of the pivot component with the LMS relies on the Learning Tools Interoperability. The validation of this approach is made through the integration of the component with LMSs from two vendors.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Optical processor based on a-SiC technology for spectral data error control

The SiC optical processor for error detection and correction is realized by using double pin/pin a-SiC:H photodetector with front and back biased optical gating elements. Data shows that the background act as selector that pick one or more states by splitting portions of the input multi optical signals across the front and back photodiodes. Boolean operations such as exclusive OR (EXOR) and three bit addition are demonstrated optically with a combination of such switching devices, showing that when one or all of the inputs are present the output will be amplified, the system will behave as an XOR gate representing the SUM. When two or three inputs are on, the system acts as AND gate indicating the present of the CARRY bit. Additional parity logic operations are performed by use of the four incoming pulsed communication channels that are transmitted and checked for errors together. As a simple example of this approach, we describe an all optical processor for error detection and correction and then, provide an experimental demonstration of this fault tolerant reversible system, in emerging nanotechnology.

Biofunctional composite coating architectures based on polycaprolactone and nanohydroxyapatite for controlled corrosion activity and enhanced biocompatibility of magnesium AZ31 alloy

In this work a biofunctional composite coating architecture for controlled corrosion activity and enhanced cellular adhesion of AZ31 Mg alloys is proposed. The composite coating consists of a polycaprolactone (PCL) matrix modified with nanohydroxyapatite (HA) applied over a nanometric layer of polyetherimide (PEI). The protective properties of the coating were studied by electrochemical impedance spectroscopy (EIS), a non-disturbing technique, and the coating morphology was investigated by field emission scanning electron microscopy (FE-SEM). The results show that the composite coating protects the AZ31 substrate. The barrier properties of the coating can be optimized by changing the PCL concentration. The presence of nanohydroxyapatite particles influences the coating morphology and decreases the corrosion resistance. The biocompatibility was assessed by studying the response of osteoblastic cells on coated samples through resazurin assay, confocal laser scanning microscopy (CLSM) and scanning electron microscopy (SEM). The results show that the polycaprolactone to hydroxyapatite ratio affects the cell behavior and that the presence of hydroxyapatite induces high osteoblastic differentiation. (C) 2014 Elsevier B.V. All rights reserved.