Mechanical behaviour of laminated functionally graded fibre-reinforced self-compacting cementitious composites

El hormigón autocompactante (HAC) es una nueva tipología de hormigón o material compuesto base cemento que se caracteriza por ser capaz de fluir en el interior del encofrado o molde, llenándolo de forma natural, pasando entre las barras de armadura y consolidándose únicamente bajo la acción de su peso propio, sin ayuda de medios de compactación externos, y sin que se produzca segregación de sus componentes. Debido a sus propiedades frescas (capacidad de relleno, capacidad de paso, y resistencia a la segregación), el HAC contribuye de forma significativa a mejorar la calidad de las estructuras así como a abrir nuevos campos de aplicación del hormigón. Por otra parte, la utilidad del hormigón reforzado con fibras de acero (HRFA) es hoy en día incuestionable debido a la mejora significativa de sus propiedades mecánicas tales como resistencia a tracción, tenacidad, resistencia al impacto o su capacidad para absorber energía. Comparado con el HRFA, el hormigón autocompactante reforzado con fibras de acero (HACRFA) presenta como ventaja una mayor fluidez y cohesión ofreciendo, además de unas buenas propiedades mecánicas, importantes ventajas en relación con su puesta en obra. El objetivo global de esta tesis doctoral es el desarrollo de nuevas soluciones estructurales utilizando materiales compuestos base cemento autocompactantes reforzados con fibras de acero. La tesis presenta una nueva forma de resolver el problema basándose en el concepto de los materiales gradiente funcionales (MGF) o materiales con función gradiente (MFG) con el fin de distribuir de forma eficiente las fibras en la sección estructural. Para ello, parte del HAC se sustituye por HACRFA formando capas que presentan una transición gradual entre las mismas con el fin de obtener secciones robustas y exentas de tensiones entre capas con el fin de aplicar el concepto “MGF-laminados” a elementos estructurales tales como vigas, columnas, losas, etc. El proceso incluye asimismo el propio método de fabricación que, basado en la tecnología HAC, permite el desarrollo de interfases delgadas y robustas entre capas (1-3 mm) gracias a las propiedades reológicas del material. Para alcanzar dichos objetivos se ha llevado a cabo un amplio programa experimental cuyas etapas principales son las siguientes: • Definir y desarrollar un método de diseño que permita caracterizar de forma adecuada las propiedades mecánicas de la “interfase”. Esta primera fase experimental incluye: o las consideraciones generales del propio método de fabricación basado en el concepto de fabricación de materiales gradiente funcionales denominado “reología y gravedad”, o las consideraciones específicas del método de caracterización, o la caracterización de la “interfase”. • Estudiar el comportamiento mecánico sobre elementos estructurales, utilizando distintas configuraciones de MGF-laminado frente a acciones tanto estáticas como dinámicas con el fin de comprobar la viabilidad del material para ser usado en elementos estructurales tales como vigas, placas, pilares, etc. Los resultados indican la viabilidad de la metodología de fabricación adoptada, así como, las ventajas tanto estructurales como en reducción de costes de las soluciones laminadas propuestas. Es importante destacar la mejora en términos de resistencia a flexión, compresión o impacto del hormigón autocompactante gradiente funcional en comparación con soluciones de HACRFA monolíticos inclusos con un volumen neto de fibras (Vf) doble o superior. Self-compacting concrete (SCC) is an important advance in the concrete technology in the last decades. It is a new type of high performance concrete with the ability of flowing under its own weight and without the need of vibrations. Due to its specific fresh or rheological properties, such as filling ability, passing ability and segregation resistance, SCC may contribute to a significant improvement of the quality of concrete structures and open up new field for the application of concrete. On the other hand, the usefulness of steel fibre-reinforced concrete (SFRC) in civil engineering applications is unquestionable. SFRC can improve significantly the hardened mechanical properties such as tensile strength, impact resistance, toughness and energy absorption capacity. Compared to SFRC, self-compacting steel fibre-reinforced concrete (SCSFRC) is a relatively new type of concrete with high flowability and good cohesiveness. SCSFRC offers very attractive economical and technical benefits thanks to SCC rheological properties, which can be further extended, when combined with SFRC for improving their mechanical characteristics. However, for the different concrete structural elements, a single concrete mix is selected without an attempt to adapt the diverse fibre-reinforced concretes to the stress-strain sectional properly. This thesis focused on the development of high performance cement-based structural composites made of SCC with and without steel fibres, and their applications for enhanced mechanical properties in front of different types of load and pattern configurations. It presents a new direction for tackling the mechanical problem. The approach adopted is based on the concept of functionally graded cementitious composite (FGCC) where part of the plain SCC is strategically replaced by SCSFRC in order to obtain laminated functionally graded self-compacting cementitious composites, laminated-FGSCC, in single structural elements as beams, columns, slabs, etc. The approach also involves a most suitable casting method, which uses SCC technology to eliminate the potential sharp interlayer while easily forming a robust and regular reproducible graded interlayer of 1-3 mm by controlling the rheology of the mixes and using gravity at the same time to encourage the use of the powerful concept for designing more performance suitable and cost-efficient structural systems. To reach the challenging aim, a wide experimental programme has been carried out involving two main steps: • The definition and development of a novel methodology designed for the characterization of the main parameter associated to the interface- or laminated-FGSCC solutions: the graded interlayer. Work of this first part includes: o the design considerations of the innovative (in the field of concrete) production method based on “rheology and gravity” for producing FG-SCSFRC or as named in the thesis FGSCC, casting process and elements, o the design of a specific testing methodology, o the characterization of the interface-FGSCC by using the so designed testing methodology. • The characterization of the different medium size FGSCC samples under different static and dynamic loads patterns for exploring their possibilities to be used for structural elements as beams, columns, slabs, etc. The results revealed the efficiency of the manufacturing methodology, which allow creating robust structural sections, as well as the feasibility and cost effectiveness of the proposed FGSCC solutions for different structural uses. It is noticeable to say the improvement in terms of flexural, compressive or impact loads’ responses of the different FGSCC in front of equal strength class SCSFRC bulk elements with at least the double of overall net fibre volume fraction (Vf).

A component- and connector-based approach for end-user composite web applications development

Enabling real end-user development is the next logical stage in the evolution of Internet-wide service-based applications. Successful composite applications rely on heavyweight service orchestration technologies that raise the bar far above end-user skills. This weakness can be attributed to the fact that the composition model does not satisfy end-user needs rather than to the actual infrastructure technologies. In our opinion, the best way to overcome this weakness is to offer end-to-end composition from the user interface to service invocation, plus an understandable abstraction of building blocks and a visual composition technique empowering end users to develop their own applications. In this paper, we present a visual framework for end users, called FAST, which fulfils this objective. FAST implements a novel composition model designed to empower non-programmer end users to create and share their own self-service composite applications in a fully visual fashion. We projected the development environment implementing this model as part of the European FP7 FAST Project, which was used to validate the rationale behind our approach.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Self-Learning Embedded System for Object Identification in Intelligent Infrastructure Sensors

The emergence of new horizons in the field of travel assistant management leads to the development of cutting-edge systems focused on improving the existing ones. Moreover, new opportunities are being also presented since systems trend to be more reliable and autonomous. In this paper, a self-learning embedded system for object identification based on adaptive-cooperative dynamic approaches is presented for intelligent sensor’s infrastructures. The proposed system is able to detect and identify moving objects using a dynamic decision tree. Consequently, it combines machine learning algorithms and cooperative strategies in order to make the system more adaptive to changing environments. Therefore, the proposed system may be very useful for many applications like shadow tolls since several types of vehicles may be distinguished, parking optimization systems, improved traffic conditions systems, etc.

Self-antigen does not accelerate immature B cell apoptosis, but stimulates receptor editing as a consequence of developmental arrest

In pre-B lymphocytes, productive rearrangement of Ig light chain genes allows assembly of the B cell receptor (BCR), which selectively promotes further developmental maturation through poorly defined transmembrane signaling events. Using a novel in vitro system to study immune tolerance during development, we find that BCR reactivity to auto-antigen blocks this positive selection, preventing down-regulation of light chain gene recombination and promoting secondary light chain gene rearrangements that often alter BCR specificity, a process called receptor editing. Under these experimental conditions, self-antigen induces secondary light chain gene rearrangements in at least two-thirds of autoreactive immature B cells, but fails to accelerate cell death at this stage. These data suggest that in these cells the mechanism of immune tolerance is receptor selection rather than clonal selection.

Inhibition of intrathymic T cell development by expression of a transgenic antagonist peptide

The mature T cell receptor (TCR) repertoire is shaped by positive- and negative-selection events taking place during T cell development. These events are regulated by interactions between the TCR and major histocompatibility complex molecules presenting self-peptides. It has been shown that many antagonist peptides are efficient at mediating positive selection. In this study we analyzed the effects of a transgene encoding an antagonist peptide (influenza NP34) that is presented by H-2Db in a Tap-1-independent fashion in mice expressing the influenza NP68-specific TCR F5. We find that the transgenic peptide does not mediate positive or negative selection in F5+Tap-1−/− mice, but inhibits maturation of CD8+ single positive thymocytes in F5+Tap-1+ mice without inducing signs of negative selection. We conclude that antagonism of antigen recognition occurs not only at the level of mature T cells but also in T cell development.

Tuning of activation thresholds explains flexibility in the selection and development of T cells in the thymus

Immature CD4+CD8+ thymocytes expressing T-cell antigen receptors (TCR) are selected by TCR-mediated recognition of peptides associated with major histocompatibility complex molecules on thymic stromal cells. Selection ensures reactivity of the mature cells to foreign antigens and tolerance to self. Although much has been learned about the factors that determine whether a thymocyte with a given specificity will be positively or negatively selected, selection as an aspect of the developmental process as a whole is less well-understood. Here we invoke a model in which thymocytes tune their response characteristics individually and dynamically in the course of development. Cellular development and selection are driven by receptor-mediated metabolic perturbations. Perturbation is a measure of the net intracellular change induced by external stimulation. It results from the integration of several signals and countersignals over time and therefore depends on the environment and the maturation stage of the cell. Individual cell adaptation limits the range of perturbations. Such adaptation renders thymocytes less sensitive to the level of stimulation per se, but responsive to environmental changes in that level. This formulation begins to explain the mechanisms that link developmental and selection events to each other.

Role of Syk in B-cell development and antigen-receptor signaling

Antigen receptors (BCRs) on developing B lymphocytes play two opposing roles—promoting survival of cells that may later bind a foreign antigen and inhibiting survival of cells that bind too strongly to self-antigens. It is not known how these opposing outcomes are signaled by BCRs on immature B cells. Here we analyze the effect of a null mutation in the Syk tyrosine kinase on maturing B cells displaying a transgene-encoded BCR that binds hen egg lysozyme (HEL). In the absence of HEL antigen, HEL-specific BCRs are expressed normally on the surface of Syk-deficient immature B-lineage cells, but this fails to promote maturation beyond the earliest stages of B-lineage commitment. Binding of HEL antigen, nevertheless, triggers phosphorylation of CD79α/β BCR subunits and modulation of receptors from the surface in Syk-deficient cells, but it cannot induce an intracellular calcium response. Continuous binding of low- or high-avidity forms of HEL, expressed as self-antigens, fails to restore the signal needed for maturation. Compared with the effects in the same system of null mutations in other BCR signaling elements, such as CD45 and Lyn kinase, these results indicate that Syk is essential for transmitting a signal that initiates the program of B-lymphocyte maturation.

Assisting developing countries toward food self-reliance

Per capita food availability in the developing world has increased by 20% since the early 1960s, according to the Food and Agriculture Organization, and today the world has twice as many people but 150 million fewer hungry people than in 1960. The world agricultural system has not done too bad a job over the past 35 years. It is likely that global agricultural production will continue to at least match growth in food demand over the next decade, assuming no major weather anomalies. Continued support of the Consultative Group for International Agricultural Research and programs involving U.S. universities is important to sharing knowledge about agriculture with colleagues in the developing world. This paper explores the reasons for providing agricultural development assistance, the benefits to the United States that come from doing so, and the special challenges facing the world over the next few decades.

γ-Secretase inhibitors repress thymocyte development

A major therapeutic target in the search for a cure to the devastating Alzheimer's disease is γ-secretase. This activity resides in a multiprotein enzyme complex responsible for the generation of Aβ42 peptides, precipitates of which are thought to cause the disease. γ-Secretase is also a critical component of the Notch signal transduction pathway; Notch signals regulate development and differentiation of adult self-renewing cells. This has led to the hypothesis that therapeutic inhibition of γ-secretase may interfere with Notch-related processes in adults, most alarmingly in hematopoiesis. Here, we show that application of γ-secretase inhibitors to fetal thymus organ cultures interferes with T cell development in a manner consistent with loss or reduction of Notch1 function. Progression from an immature CD4−/CD8− state to an intermediate CD4+/CD8+ double-positive state was repressed. Furthermore, treatment beginning later at the double-positive stage specifically inhibited CD8+ single-positive maturation but did not affect CD4+ single-positive cells. These results demonstrate that pharmacological γ-secretase inhibition recapitulates Notch1 loss in a vertebrate tissue and present a system in which rapid evaluation of γ-secretase-targeted pharmaceuticals for their ability to inhibit Notch activity can be performed in a relevant context.

Systemic immunization with papillomavirus L1 protein completely prevents the development of viral mucosal papillomas.

Infection of mucosal epithelium by papillomaviruses is responsible for the induction of genital and oral warts and plays a critical role in the development of human cervical and oropharyngeal cancer. We have employed a canine model to develop a systemic vaccine that completely protects against experimentally induced oral mucosal papillomas. The major capsid protein, L1, of canine oral papillomavirus (COPV) was expressed in Sf9 insect cells in native conformation. L1 protein, which self-assembled into virus-like particles, was purified on CsCl gradients and injected intradermally into the foot pad of beagles. Vaccinated animals developed circulating antibodies against COPV and became completely resistant to experimental challenge with COPV. Successful immunization was strictly dependent upon native L1 protein conformation and L1 type. Partial protection was achieved with as little as 0.125 ng of L1 protein, and adjuvants appeared useful for prolonging the host immune response. Serum immunoglobulins passively transferred from COPV L1-immunized beagles to naive beagles conferred protection from experimental infection with COPV. Our results indicate the feasibility of developing a human vaccine to prevent mucosal papillomas, which can progress to malignancy.

Invariance and restriction toward a limited set of self-antigens characterize neonatal IgM antibody repertoires and prevail in autoreactive repertoires of healthy adults.

Analysis of the reactivity of IgM with self-antigens in tissues by a quantitative immunoblotting technique showed striking invariance among newborns in the human and in the mouse. The self-reactive repertoire of IgM of adults was also markedly conserved; it comprised most anti-self reactivities that prevailed among neonates. Multivariate analysis confirmed the homogeneity of IgM repertoires of neonates toward self- and non-self-antigens. Multivariate analysis discriminated between newborn and adult repertoires for reactivity with two of five sources of self-proteins and with non-self-antigens. Our observations support the concept that naturally activated B lymphocytes are selected early in development and throughout life for reactivity with a restricted set of self-antigens.

Prospect for development of Open Access in Argentina

This perspective article presents an overview of the Open Access movement in Argentina, from a global and regional (Latin American) context. The article describes the evolution and current state of initiatives by examining two principal approaches to Open Access in Argentina: golden and green roads. The article will then turn its attention to: the support that Open Access receives from governmental sources; collaboration with international projects; and the perspective of Argentine authors regarding Open Access and self-archiving. It concludes with a reflection on the outlook, the main barriers and opportunities for Open Access in Argentina

The role of the social environment in non-suicidal self-injury among LGBTQ youth: A mixed methods study

Non-suicidal self-injury (NSSI), such as cutting and burning, is a widespread social problem among lesbian, gay, bisexual, transgender, queer, and questioning (LGBTQ) youth. Extant research indicates that this population is more than twice as likely to engage in NSSI than heterosexual and cisgender (non-transgender) youth. Despite the scope of this social problem, it remains relatively unexamined in the literature. Research on other risk behaviors among LGBTQ youth indicates that experiencing homophobia and transphobia in key social contexts such as families, schools, and peer relationships contributes to health disparities among this group. Consequently, the aims of this study were to examine: (1) the relationship between LGBTQ youth's social environments and their NSSI behavior, and (2) whether/how specific aspects of the social environment contribute to an understanding of NSSI among LGBTQ youth. This study was conducted using an exploratory, sequential mixed methods design with two phases. The first phase of the study involved analysis of transcripts from interviews conducted with 44 LGBTQ youth recruited from a community-based organization. In this phase, five qualitative themes were identified: (1) Violence; (2) Misconceptions, Stigma, and Shame; (3) Negotiating LGBTQ Identity; (4) Invisibility and Isolation; and (5) Peer Relationships. Results from the qualitative phase were used to identify key variables and specify statistical models in the second, quantitative, phase of the study, using secondary data from a survey of 252 LGBTQ youth. The qualitative phase revealed how LGBTQ youth, themselves, described the role of the social environment in their NSSI behavior, while the quantitative phase was used to determine whether the qualitative findings could be used to predict engagement in NSSI among a larger sample of LGBTQ youth. The quantitative analyses found that certain social-environmental factors such as experiencing physical abuse at home, feeling unsafe at school, and greater openness about sexual orientation significantly predicted the likelihood of engaging in NSSI among LGBTQ youth. Furthermore, depression partially mediated the relationships between family physical abuse and NSSI and feeling unsafe at school and NSSI. The qualitative and quantitative results were compared in the interpretation phase to explore areas of convergence and incongruence. Overall, this study's findings indicate that social-environmental factors are salient to understanding NSSI among LGBTQ youth. The particular social contexts in which LGBTQ youth live significantly influence their engagement in this risk behavior. These findings can inform the development of culturally relevant NSSI interventions that address the social realities of LGBTQ youth's lives.

Expert Approaches to Mental Toughness Development in the High Risk Sport of Diving

Research focusing on mental toughness development and high risk sport is limited to one examination of elite gymnasts' perceptions. Coaches have acknowledged that mental toughness is important to performance success, while admitting they do not know effective development strategies. The aim of the current research is to address both these concerns by employing a grounded theory approach to ascertain elite diving coaches perceptions of mental toughness development and what mental toughness is. Seven diving coaches volunteered and were interviewed for an average of 49 minutes. They all coached an athlete that participated either in the world championships or Olympic games since 2008. Participants reported that mental toughness was the ability of a diver to perform a movement in a crucial moment that requires focus, extending beyond their comfort zone, overcoming fear, and never giving up. Mentaltoughness may not be the appropriate term due to its lack of multicultural sensitivity. Participants felt that dealing with adversity was something divers would have to constantly process. Mental toughness can be developed by the coach, the environment, or individual athlete. Unique attributes specific to divers were an awareness of self and a distinct level of knowing what the athlete was going to do. More research needs to be conducted to determine if these concepts can be generalized to other high risk sports. Future research could help establish a valid quantitative measure of mental toughness development.