Distinct Disulfide Isomers of mu-Conotoxins KIIIA and KIIIB Block Voltage-Gated Sodium Channels

In the preparation of synthetic conotoxins containing multiple disulfide bonds, oxidative folding can produce numerous permutations of disulfide bond connectivities. Establishing the native disulfide connectivities thus presents a significant challenge when the venom-derived peptide is not available, as is increasingly the case when conotoxins are identified from cDNA sequences. Here, we investigate the disulfide connectivity of mu-conotoxin KIIIA, which was predicted originally to have a C1-C9,C2-C15,C4-C16] disulfide pattern based on homology with closely related mu-conotoxins. The two major isomers of synthetic mu-KIIIA formed during oxidative folding were purified and their disulfide connectivities mapped by direct mass spectrometric collision-induced dissociation fragmentation of the disulfide-bonded polypeptides. Our results show that the major oxidative folding product adopts a C1-C15,C2-C9,C4-C16] disulfide connectivity, while the minor product adopts a C1-C16,C2-C9,C4-C15] connectivity. Both of these peptides were potent blockers of Na(v)1.2 (K-d values of 5 and 230 nM, respectively). The solution structure for mu-KIIIA based on nuclear magnetic resonance data was recalculated with the C1-C15,C2-C9,C4-C16] disulfide pattern; its structure was very similar to the mu-KIIIA structure calculated with the incorrect C1-C9,C2-C15,C4-C16] disulfide pattern, with an alpha-helix spanning residues 7-12. In addition, the major folding isomers of mu-KIIIB, an N-terminally extended isoform of mu-KIIIA, identified from its cDNA sequence, were isolated. These folding products had the same disulfide connectivities as mu-KIIIA, and both blocked Na(v)1.2 (K-d values of 470 and 26 nM, respectively). Our results establish that the preferred disulfide pattern of synthetic mu-KIIIA and mu-KIIIB folded in vitro is 1-5/2-4/3-6 but that other disulfide isomers are also potent sodium channel blockers. These findings raise questions about the disulfide pattern(s) of mu-KIIIA in the venom of Conus kinoshitai; indeed, the presence of multiple disulfide isomers in the venom could provide a means of further expanding the snail's repertoire of active peptides.

Interaction Signatures Stabilizing the NAD(P)-Binding Rossmann Fold: A Structure Network Approach

The fidelity of the folding pathways being encoded in the amino acid sequence is met with challenge in instances where proteins with no sequence homology, performing different functions and no apparent evolutionary linkage, adopt a similar fold. The problem stated otherwise is that a limited fold space is available to a repertoire of diverse sequences. The key question is what factors lead to the formation of a fold from diverse sequences. Here, with the NAD(P)-binding Rossmann fold domains as a case study and using the concepts of network theory, we have unveiled the consensus structural features that drive the formation of this fold. We have proposed a graph theoretic formalism to capture the structural details in terms of the conserved atomic interactions in global milieu, and hence extract the essential topological features from diverse sequences. A unified mathematical representation of the different structures together with a judicious concoction of several network parameters enabled us to probe into the structural features driving the adoption of the NAD(P)-binding Rossmann fold. The atomic interactions at key positions seem to be better conserved in proteins, as compared to the residues participating in these interactions. We propose a ``spatial motif'' and several ``fold specific hot spots'' that form the signature structural blueprints of the NAD(P)-binding Rossmann fold domain. Excellent agreement of our data with previous experimental and theoretical studies validates the robustness and validity of the approach. Additionally, comparison of our results with statistical coupling analysis (SCA) provides further support. The methodology proposed here is general and can be applied to similar problems of interest.

SEU Tolerant Robust Memory Cell Design

The implementation of semiconductor circuits and systems in nano-technology makes it possible to achieve high speed, lower voltage level and smaller area. The unintended and undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by alpha particle or neutron hits. These events of radiation strike resulting into bit upsets referred to as single event upsets(SEU), become increasingly of concern for the reliable circuit operation in the field. Storage elements are worst hit by this phenomenon. As we further scale down, there is greater interest in reliability of the circuits and systems, apart from the performance, power and area aspects. In this paper we propose an improved 12T SEU tolerant SRAM cell design. The proposed SRAM cell is economical in terms of area overhead. It is easy to fabricate as compared to earlier designs. Simulation results show that the proposed cell is highly robust, as it does not flip even for a transient pulse with 62 times the Q(crit) of a standard 6T SRAM cell.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

Switching of a Sixteen Electrode Array for Wireless EIT System Using a RF-Based 8-Bit Digital Data Transmission Technique

Surface electrode switching of 16-electrode wireless EIT is studied using a Radio Frequency (RF) based digital data transmission technique operating with 8 channel encoder/decoder ICs. An electrode switching module is developed the analog multiplexers and switched with 8-bit parallel digital data transferred by transmitter/receiver module developed with radio frequency technology. 8-bit parallel digital data collected from the receiver module are converted to 16-bit digital data by using binary adder circuits and then used for switching the electrodes in opposite current injection protocol. 8-bit parallel digital data are generated using NI USB 6251 DAQ card in LabVIEW software and sent to the transmission module which transmits the digital data bits to the receiver end. Receiver module supplies the parallel digital bits to the binary adder circuits and adder circuit outputs are fed to the multiplexers of the electrode switching module for surface electrode switching. 1 mA, 50 kHz sinusoidal constant current is injected at the phantom boundary using opposite current injection protocol. The boundary potentials developed at the voltage electrodes are measured and studied to assess the wireless data transmission.

Multilevel Dodecagonal Voltage Space Vector Generation using Flying Capacitor topology for Induction motor drives

In this paper, a multilevel flying capacitor inverter topology suitable for generating multilevel dodecagonal space vectors for an induction motor drive, is proposed. Because of the dodecagonal space vectors, it has increased modulation range with the absence of all 6n +/- 1, (n=odd) harmonics in the phase voltage and currents. The topology, realized by flying capacitor three level inverters feeding an open-end winding induction motor, does not suffer the neutral point voltage imbalance issues seen in NPC inverters and the capacitors have inherent charge-balancing capability with PWM control using switching state redundancies. Furthermore, the proposed technique uses lesser number of power supplies compared to cascaded H-bridge or NPC based dodecagonal schemes and has better ride-through capability. Finally, the voltage control is obtained through a simple carrier-based space vector PWM scheme implemented on a DSP.

Evaluation of dynamic voltage and frequency scaling for stream programs

Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing trade-offs involving energy, power, temperature and performance of computing systems. In this paper, we evaluate three different DVFS schemes - our enhancement of a Petri net performance model based DVFS method for sequential programs to stream programs, a simple profile based Linear Scaling method, and an existing hardware based DVFS method for multithreaded applications - using multithreaded stream applications, in a full system Chip Multiprocessor (CMP) simulator. From our evaluation, we find that the software based methods achieve significant Energy/Throughput2(ET−2) improvements. The hardware based scheme degrades performance heavily and suffers ET−2 loss. Our results indicate that the simple profile based scheme achieves the benefits of the complex Petri net based scheme for stream programs, and present a strong case for the need for independent voltage/frequency control for different cores of CMPs, which is lacking in most of the state-of-the-art CMPs. This is in contrast to the conclusions of a recent evaluation of per-core DVFS schemes for multithreaded applications for CMPs.

A Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage IM Drives

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n +/- 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including over-modulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally.

Medium Voltage Drive for Induction Motors Using Multilevel Octadecagonal Voltage Space Vectors

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n +/- 1 (n = odd) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation.

Correlation between corona current and radio interference due to high voltage insulator string

The Radio Interference (RI) from electric power transmission line hardware, if not controlled, poses serious electromagnetic interference to system in the vicinity. The present work mainly concerns with the RI from the insulator string along with the associated line hardware. The laboratory testing for the RI levels are carried out through the measurement of the conducted radio interference levels. However such measurements do not really locate the coronating point, as well as, the mode of corona. At the same time experience shows that it is rather difficult to locate the coronating points by mere inspection. After a thorough look into the intricacies of the problem, it is ascertained that the measurement of associated ground end currents could give a better picture of the prevailing corona modes and their intensities. A study on the same is attempted in the present work. Various intricacies of the problem,features of ground end current pulses and its correlation with RI are dealt with. Owing to the complexity of such experimental investigations, the study made is not fully complete nevertheless it seems to be first of its kind.

Comparison of 3-phase, 3-level UPF rectifier circuits for high power applications

This paper presents an analysis and comparison between two circuit topologies of the 3-phase, 3-level unity power factor (Vienna) rectifier on the basis of packaging issues and semiconductor power losses. The analysis indicates the suitability of one particular circuit variant due to restrictions on switching frequency at higher power levels. A comparison is also done between hysteresis and carrier based PWM strategies for current control of the rectifier, along with experimental evaluation of the control strategies on a hardware prototype of the rectifier. The comparison indicates that the carrier based modulation strategy is better suited for use with higher order filters that are utilized in high power applications.