Customs-Related Transaction Costs, Firm Size and International Trade Intensity

Customs are generally perceived as a time-consuming impediment to international trade. However, few studies have empirically examined the determinants and the impact of this type of government-imposed transaction costs. This paper analyses the role of firm size as a determinant of customs-related transaction costs, as well as the effect of firm size on the relationship between these costs and the international trade intensity of firms. The results of this study indicate that customs-related transaction costs repress international trade activities of firms, even at low levels of these costs. The paper identifies transaction-related economies of scale, simplified customs procedures and advanced information and communication technology as main determinants of customs-related transaction costs. It is shown that when these factors are taken into account, firm size has no effect on customs-related transaction costs. Policy implications are considered for firm strategy and public policy.

Controlling the Shadow Trade

From tackling illicit flows of small arms to combating nuclear smuggling, the shadow trade has become a central target of attempts to control the means of violence. This article argues that much of this practice and literature is framed in unhelpful terms that posit two distinct worlds, an upperworld and underworld, that separates illicit flow networks from the familiar world of state security policy. This implies that the possibilities for controlling the shadow trade are limited or require expansive and expensive controls. The article then examines the formation of illicit flow networks, drawing on examples including narcotics, small arms, nuclear materials, nuclear technology, major conventional arms, dual use technologies, and chemical weapons precursors; and finds that state and hybrid actors rather than extensive private networks are constitutive of illicit networks in many ways. It concludes by reclaiming hope for controlling the means of violence in this hybridity.

Non Classical Design in MOSFETs for Improving OTA gain-bandwidth trade off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain along with three times higher cutoff frequency as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle ratio of 3.2 and operated below a bias current of 80 microamps demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology. Index Terms—Analog/RF, double gate, gain-bandwidth product, .

Bad Faith in European Trade Mark Law

Analyses how the European Court of Justice has interpreted the EU law rules against the registration of a trade mark or Community trade mark by an applicant in bad faith. Reviews case law from the UK courts, Office of Harmonisation in the Internal Market and Community courts on the role of bad faith as a moral standard. Considers case law on the narrow interpretation of bad faith in view of other EU provisions limiting trade marks.

A Capabilities-Aware Framework for Using Computational Accelerators in Data-Intensive Computing

Multicore computational accelerators such as GPUs are now commodity components for highperformance computing at scale. While such accelerators have been studied in some detail as stand-alone computational engines, their integration in large-scale distributed systems raises new challenges and trade-offs. In this paper, we present an exploration of resource management alternatives for building asymmetric accelerator-based distributed systems. We present these alternatives in the context of a capabilities-aware framework for data-intensive computing, which uses an enhanced implementation of the MapReduce programming model for accelerator-based clusters, compared to the state of the art. The framework can transparently utilize heterogeneous accelerators for deriving high performance with low programming effort. Our work is the first to compare heterogeneous types of accelerators, GPUs and a Cell processors, in the same environment and the first to explore the trade-offs between compute-efficient and control-efficient accelerators on data-intensive systems. Our investigation shows that our framework scales well with the number of different compute nodes. Furthermore, it runs simultaneously on two different types of accelerators, successfully adapts to the resource capabilities, and performs 26.9% better on average than a static execution approach.

Prediction-Based Power-Performance Adaptation of Multithreaded Scientific Codes

Computing has recently reached an inflection point with the introduction of multicore processors. On-chip thread-level parallelism is doubling approximately every other year. Concurrency lends itself naturally to allowing a program to trade performance for power savings by regulating the number of active cores; however, in several domains, users are unwilling to sacrifice performance to save power. We present a prediction model for identifying energy-efficient operating points of concurrency in well-tuned multithreaded scientific applications and a runtime system that uses live program analysis to optimize applications dynamically. We describe a dynamic phase-aware performance prediction model that combines multivariate regression techniques with runtime analysis of data collected from hardware event counters to locate optimal operating points of concurrency. Using our model, we develop a prediction-driven phase-aware runtime optimization scheme that throttles concurrency so that power consumption can be reduced and performance can be set at the knee of the scalability curve of each program phase. The use of prediction reduces the overhead of searching the optimization space while achieving near-optimal performance and power savings. A thorough evaluation of our approach shows a reduction in power consumption of 10.8 percent, simultaneous with an improvement in performance of 17.9 percent, resulting in energy savings of 26.7 percent.