Highly sensitive, localized surface plasmon resonance fiber device for environmental sensing, based upon a structured bi-metal array of nano-wires

We demonstrate a bi-metal coated (platinum and gold or silver), localized surface plasmon resonance fiber sensor with an index sensitivity exceeding 11,900 nm/RIU, yielding an index resolution of 2 × 10-5 in the aqueous index regime. This is one of the highest index sensitivities achieved with an optical fiber sensor. The coatings consist of arrays of bi-metal nano-wires (typically 36 nm in radius and 20 μm in length), supported by a silicon dioxide thin film on a thin substrate of germanium, the nano-wires being perpendicular to the longitudinal axis of the D-shaped fiber.

Pore confinement effects and stabilization of carbon nitride oligomers in macroporous silica for photocatalytic hydrogen production

An ordered macroporous host (mac-SiO2) has been used to prevent aggregation of layered photocatalysts based on carbon nitride. Using typical carbon nitride synthesis conditions, cyanamide was condensed at 550 °C in the presence and absence of mac-SiO2. Condensation in the absence of mac-SiO2 results in materials with structural characteristics consistent with the carbon nitride, melon, accompanied by ca. 2 wt% carbonization. For mac-SiO2 supported materials, condensation occurs with greater carbonization (ca. 6 wt%). On addition of 3 wt% Pt cocatalyst photocatalytic hydrogen production under visible light is found to be up to 10 times greater for the supported composites. Time-resolved photoluminescence spectroscopy shows that excited state relaxation is more rapid for the mac-SiO2 supported materials suggesting faster electron-hole recombination and that supported carbon nitride does not exhibit improved charge separation. CO2 temperature programmed desorption indicates that enhanced photoactivity of supported carbon nitride is attributable to an increased surface area compared to bulk carbon nitride and an increase in the concentration of weakly basic catalytic sites, consistent with carbon nitride oligomers.

Silicon photonic device for wavelength sensing and monitoring

Over the last decade advances and innovations from Silicon Photonics technology were observed in the telecommunications and computing industries. This technology which employs Silicon as an optical medium, relies on current CMOS micro-electronics fabrication processes to enable medium scale integration of many nano-photonic devices to produce photonic integrated circuitry. ^ However, other fields of research such as optical sensor processing can benefit from silicon photonics technology, specially in sensors where the physical measurement is wavelength encoded. ^ In this research work, we present a design and application of a thermally tuned silicon photonic device as an optical sensor interrogator. ^ The main device is a micro-ring resonator filter of 10 μm of diameter. A photonic design toolkit was developed based on open source software from the research community. With those tools it was possible to estimate the resonance and spectral characteristics of the filter. From the obtained design parameters, a 7.8 × 3.8 mm optical chip was fabricated using standard micro-photonics techniques. In order to tune a ring resonance, Nichrome micro-heaters were fabricated on top of the device. Some fabricated devices were systematically characterized and their tuning response were determined. From measurements, a ring resonator with a free-spectral-range of 18.4 nm and with a bandwidth of 0.14 nm was obtained. Using just 5 mA it was possible to tune the device resonance up to 3 nm. ^ In order to apply our device as a sensor interrogator in this research, a model of wavelength estimation using time interval between peaks measurement technique was developed and simulations were carried out to assess its performance. To test the technique, an experiment using a Fiber Bragg grating optical sensor was set, and estimations of the wavelength shift of this sensor due to axial strains yield an error within 22 pm compared to measurements from spectrum analyzer. ^ Results from this study implies that signals from FBG sensors can be processed with good accuracy using a micro-ring device with the advantage of ts compact size, scalability and versatility. Additionally, the system also has additional applications such as processing optical wavelength shifts from integrated photonic sensors and to be able to track resonances from laser sources.^

Surrey-Hampshire border ware ceramics in seventeenth-century English North America

During the sixteenth and seventeenth centuries, Surrey-Hampshire Border ware ceramics were among of the most popular and widely used ceramics in southern England. This ceramic, produced along the Surrey-Hampshire border, was also shipped to English colonies in North America throughout the seventeenth century. This thesis will explore the types of vessels uncovered on archaeological sites in Newfoundland, New England and the Chesapeake, and examine the similarities and differences in the forms available to various colonists during this time period. By comparing the collections of Border ware found at various sites it is possible to not only determine what vessel forms are present in Northeastern English North America, but to determine the similarities and differences in vessels based on temporal, geographic, social or economic factors. A comparative study of Border ware also provides information on the socio-economic status of the colonists and on trading networks between England and North America during the seventeenth century.

Study of Periodic and Quasi-Periodic Structures in Silicon-on-Insulator

In this thesis, a numerical design approach has been proposed and developed based on the transmission matrix method in order to characterize periodic and quasi-periodic photonic structures in silicon-on-insulator. The approach and its performance have been extensively tested with specific structures in 2D and its validity has been verified in 3D.

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Piezoelectric energy harvesting using blood-flow-like excitation for implantable devices

The goal of this research is to produce a system for powering medical implants to increase the lifetime of the implanted devices and reduce the battery size. The system consists of a number of elements – the piezoelectric material for generating power, the device design, the circuit for rectification and energy storage. The piezoelectric material is analysed and a process for producing a repeatable high quality piezoelectric material is described. A full width half maximum (FWHM) of the rocking curve X-Ray diffraction (XRD) scan of between ~1.5° to ~1.7° for test wafers was achieved. This is state of the art for AlN on silicon and means devices with good piezoelectric constants can be fabricated. Finite element modelling FEM) was used to design the structures for energy harvesting. The models developed in this work were established to have an accuracy better than 5% in terms of the difference between measured and modelled results. Devices made from this material were analysed for power harvesting ability as well as the effect that they have on the flow of liquid which is an important consideration for implantable devices. The FEM results are compared to experimental results from laser Doppler vibrometry (LDV), magnetic shaker and perfusion machine tests. The rectifying circuitry for the energy harvester was also investigated. The final solution uses multiple devices to provide the power to augment the battery and so this was a key feature to be considered. Many circuits were examined and a solution based on a fully autonomous circuit was advanced. This circuit was analysed for use with multiple low power inputs similar to the results from previous investigations into the energy harvesting devices. Polymer materials were also studied for use as a substitute for the piezoelectric material as well as the substrate because silicon is more brittle.

A low overhead error confinement method based on application statistical characteristics

Reliability has emerged as a critical design constraint especially in memories. Designers are going to great lengths to guarantee fault free operation of the underlying silicon by adopting redundancy-based techniques, which essentially try to detect and correct every single error. However, such techniques come at a cost of large area, power and performance overheads which making many researchers to doubt their efficiency especially for error resilient systems where 100% accuracy is not always required. In this paper, we present an alternative method focusing on the confinement of the resulting output error induced by any reliability issues. By focusing on memory faults, rather than correcting every single error the proposed method exploits the statistical characteristics of any target application and replaces any erroneous data with the best available estimate of that data. To realize the proposed method a RISC processor is augmented with custom instructions and special-purpose functional units. We apply the method on the proposed enhanced processor by studying the statistical characteristics of the various algorithms involved in a popular multimedia application. Our experimental results show that in contrast to state-of-the-art fault tolerance approaches, we are able to reduce runtime and area overhead by 71.3% and 83.3% respectively.

Dielectric screening in atomically thin boron nitride nanosheets

Two-dimensional (2D) hexagonal boron nitride (BN) nanosheets are excellent dielectric substrate for graphene, molybdenum disulfide, and many other 2D nanomaterial-based electronic and photonic devices. To optimize the performance of these 2D devices, it is essential to understand the dielectric screening properties of BN nanosheets as a function of the thickness. Here, electric force microscopy along with theoretical calculations based on both state-of-the-art first-principles calculations with van der Waals interactions under consideration, and nonlinear Thomas-Fermi theory models are used to investigate the dielectric screening in high-quality BN nanosheets of different thicknesses. It is found that atomically thin BN nanosheets are less effective in electric field screening, but the screening capability of BN shows a relatively weak dependence on the layer thickness.

Investigating routes toward atomic layer deposition of silicon carbide: Ab initio screening of potential silicon and carbon precursors

Silicon carbide (SiC) is a promising material for electronics due to its hardness, and ability to carry high currents and high operating temperature. SiC films are currently deposited using chemical vapor deposition (CVD) at high temperatures 1500–1600 °C. However, there is a need to deposit SiC-based films on the surface of high aspect ratio features at low temperatures. One of the most precise thin film deposition techniques on high-aspect-ratio surfaces that operates at low temperatures is atomic layer deposition (ALD). However, there are currently no known methods for ALD of SiC. Herein, the authors present a first-principles thermodynamic analysis so as to screen different precursor combinations for SiC thin films. The authors do this by calculating the Gibbs energy ΔGΔG of the reaction using density functional theory and including the effects of pressure and temperature. This theoretical model was validated for existing chemical reactions in CVD of SiC at 1000 °C. The precursors disilane (Si2H6), silane (SiH4), or monochlorosilane (SiH3Cl) with ethyne (C2H2), carbontetrachloride (CCl4), or trichloromethane (CHCl3) were predicted to be the most promising for ALD of SiC at 400 °C.

Functional surface chemistry of carbon-based nanostructures

The recently discovered abilities to synthesize single-walled carbon nanotubes and prepare single layer graphene have spurred interest in these sp2-bonded carbon nanostructures. In particular, studies of their potential use in electronic devices are many as silicon integrated circuits are encountering processing limitations, quantum effects, and thermal management issues due to rapid device scaling. Nanotube and graphene implementation in devices does come with significant hurdles itself. Among these issues are the ability to dope these materials and understanding what influences defects have on expected properties. Because these nanostructures are entirely all-surface, with every atom exposed to ambient, introduction of defects and doping by chemical means is expected to be an effective route for addressing these issues. Raman spectroscopy has been a proven characterization method for understanding vibrational and even electronic structure of graphene, nanotubes, and graphite, especially when combined with electrical measurements, due to a wealth of information contained in each spectrum. In Chapter 1, a discussion of the electronic structure of graphene is presented. This outlines the foundation for all sp2-bonded carbon electronic properties and is easily extended to carbon nanotubes. Motivation for why these materials are of interest is readily gained. Chapter 2 presents various synthesis/preparation methods for both nanotubes and graphene, discusses fabrication techniques for making devices, and describes characterization methods such as electrical measurements as well as static and time-resolved Raman spectroscopy. Chapter 3 outlines changes in the Raman spectra of individual metallic single-walled carbon nantoubes (SWNTs) upon sidewall covalent bond formation. It is observed that the initial degree of disorder has a strong influence on covalent sidewall functionalization which has implications on developing electronically selective covalent chemistries and assessing their selectivity in separating metallic and semiconducting SWNTs. Chapter 4 describes how optical phonon population extinction lifetime is affected by covalent functionalization and doping and includes discussions on static Raman linewidths. Increasing defect concentration is shown to decrease G-band phonon population lifetime and increase G-band linewidth. Doping only increases G-band linewidth, leaving non-equilibrium population decay rate unaffected. Phonon mediated electron scattering is especially strong in nanotubes making optical phonon decay of interest for device applications. Optical phonon decay also has implications on device thermal management. Chapter 5 treats doping of graphene showing ambient air can lead to inadvertent Fermi level shifts which exemplifies the sensitivity that sp2-bonded carbon nanostructures have to chemical doping through sidewall adsorption. Removal of this doping allows for an investigation of electron-phonon coupling dependence on temperature, also of interest for devices operating above room temperature. Finally, in Chapter 6, utilizing the information obtained in previous chapters, single carbon nanotube diodes are fabricated and characterized. Electrical performance shows these diodes are nearly ideal and photovoltaic response yields 1.4 nA and 205 mV of short circuit current and open circuit voltage from a single nanotube device. A summary and discussion of future directions in Chapter 7 concludes my work.

Contactless Spectral-Dependent Measurement of Bulk Lifetime and Surface Recombination Velocity in Silicon Photovoltaic Materials

Charge carrier lifetime measurements in bulk or unfinished photovoltaic (PV) materials allow for a more accurate estimate of power conversion efficiency in completed solar cells. In this work, carrier lifetimes in PV- grade silicon wafers are obtained by way of quasi-steady state photoconductance measurements. These measurements use a contactless RF system coupled with varying narrow spectrum input LEDs, ranging in wavelength from 460 nm to 1030 nm. Spectral dependent lifetime measurements allow for determination of bulk and surface properties of the material, including the intrinsic bulk lifetime and the surface recombination velocity. The effective lifetimes are fit to an analytical physics-based model to determine the desired parameters. Passivated and non-passivated samples are both studied and are shown to have good agreement with the theoretical model.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.