Concentration of nutrients and primary production in sea ice of the high-latitudinal Arctic

Dynamics of phosphates and silicates in sea ice of the high-latitudinal Arctic are considered for period from November 2005 to May 2006. It is shown that, during ice formation, silicates are included into it in the same ratio to salinity that is characteristic of under-ice water. Further dynamics of silicates are determined by their bioassimilation with beginning of the polar day and by biogenic silicon accumulation at bottom meltwater pools with subsequent leaching. Phosphates are included into ice in a ratio higher than that occurring in the under-ice water. This is caused by the fact that liquid phase of sea ice represents composition of the surface microlayer at the ice-water interface, which is enriched in organic matter and in products of its destruction (particularly in phosphates). With onset of the polar day, content of phosphates first markedly increases (due to photo oxidation of biogenic organic matter) and then decreases because of bioassimilation. At the beginning of the polar day, primary production of diatoms was estimated to be ~0.3 mg C/m**2/day.

Landfast sea-ice and platelet-layer thickness and conductivity of Atka Bay, Antarctica, December 2012

Ice shelves strongly impact coastal Antarctic sea-ice and the associated ecosystem through the formation of a sub-sea-ice platelet layer. Although progress has been made in determining and understanding its spatio-temporal variability based on point measurements, an investigation of this phenomenon on a larger scale remains a challenge due to logistical constraints and a lack of suitable methodology. In this study, we applied a laterally-constrained Marquardt-Levenberg inversion to a unique multi-frequency electromagnetic (EM) induction sounding dataset obtained on the landfast sea ice of Atka Bay, eastern Weddell Sea, in 2012. In addition to consistent fast-ice thickness and -conductivities along > 100 km transects; we present the first comprehensive, high resolution platelet-layer thickness and -conductivity dataset recorded on Antarctic sea ice. The reliability of the algorithm was confirmed by using synthetic data, and the inverted platelet-layer thicknesses agreed within the data uncertainty to drill-hole measurements. Ice-volume fractions were calculated from platelet-layer conductivities, revealing that an older and thicker platelet layer is denser and more compacted than a loosely attached, young platelet layer. The overall platelet-layer volume below Atka Bay fast ice suggests that the contribution of ocean/ice-shelf interaction to sea-ice volume in this region is even higher than previously thought. This study also implies that multi-frequency EM induction sounding is an effective approach in determining platelet layer volume on a larger scale than previously feasible. When applied to airborne multi-frequency EM, this method could provide a step towards an Antarctic-wide quantification of ocean/ice-shelf interaction.

Enzyme activity, body measures and heart mass of Sepia officinalis sampled in the English Channel and Adriatic Sea

In the eurythermal cuttlefish Sepia officinalis, performance depends on hearts that ensure systemic oxygen supply over a broad range of temperatures. We therefore aimed to identify adjustments in energetic cardiac capacity and underlying mitochondrial function supporting thermal acclimation and adaptation that could be crucial for the cuttlefish's competitive success in variable environments. Two genetically distinct cuttlefish populations were acclimated to 11, 16 and 21°C. Subsequently, skinned and permeabilised heart fibres were used to assess mitochondrial functioning by means of high-resolution respirometry and a substrate-inhibitor protocol, followed by measurements of cardiac citrate synthase and cytosolic enzyme activities. Temperate English Channel cuttlefish had lower mitochondrial capacities but larger hearts than subtropical Adriatic cuttlefish. Warm acclimation to 21°C decreased mitochondrial complex I activity in Adriatic cuttlefish and increased complex IV activity in English Channel cuttlefish. However, compensation of mitochondrial capacities did not occur during cold acclimation to 11°C. In systemic hearts, the thermal sensitivity of mitochondrial substrate oxidation was high for proline and pyruvate but low for succinate. Oxygen efficiency of catabolism rose as temperature changed from 11 to 21°C via shifts to oxygen-conserving oxidation of proline and pyruvate and via reduced relative proton leak. The changes observed for substrate oxidation, mitochondrial complexes, relative proton leak and heart mass improve energetic efficiency and essentially seem to extend tolerance to high temperatures and reduce associated tissue hypoxia. We conclude that cuttlefish sustain cardiac performance and, thus, systemic oxygen delivery over short- and long-term changes of temperature and environmental conditions by multiple adjustments in cellular and mitochondrial energetics.

(Table 1) Grain size parameters of intertidal channel sand bars near Sylt, North-Frisian Wadden Sea

The aim of the present study is to investigate directional asymmetric properties and internal structures of the bedforms on the intertidal sand bars in comparison with the migration problems of the sand bodies developed in the channel systems of the tidal basin off the west coast of Schleswig-Holstein. The tidal channel sand bodies studied have 'V'-shaped outlines and are asymmetric in cross-section. Based on such knowledge it was hoped to understand and find possible factors for application to recent and ancient tidal depositional environments. The V-shaped intertidal channel sand bodies developed in the tidal environments between Sylt and Föhr Island are constantly migrating sand bars. The migration directions are in good agreement with the resultant vector mean directions of internal cross-stratification structures of asymmetric sedimentary bedforms. Finally, it is shown that the orientation of the apex of V-shaped sand bar as an equilibrium form alone can not indicate the migration direction, but that the orientation of the resultant vector mean of internal structures of sedimentary bedforms does indicate the migration direction. Based on the analyses of textural parameters of the migrating intertidal bar sands, it seems that sands of typical intertidal sand bars are negatively skewed and well sorted. The high rounding of quarz sand grains of these tidal channel sand bars seems to be an additional characteristical criterion for tidal depositional environments, as also indicated by Balazs and Klein (1972).

Temperature time series and physical properties of snow samples of a high-arctic permafrost site on Svalbard, Norway

Independent measurements of radiation, sensible and latent heat fluxes and the ground heat flux are used to describe the annual cycle of the surface energy budget at a high-arctic permafrost site on Svalbard. During summer, the net short-wave radiation is the dominant energy source, while well developed turbulent processes and the heat flux in the ground lead to a cooling of the surface. About 15% of the net radiation is consumed by the seasonal thawing of the active layer in July and August. The Bowen ratio is found to vary between 0.25 and 2, depending on water content of the uppermost soil layer. During the polar night in winter, the net long-wave radiation is the dominant energy loss channel for the surface, which is mainly compensated by the sensible heat flux and, to a lesser extent, by the ground heat flux, which originates from the refreezing of the active layer. The average annual sensible heat flux of -6.9 W/m**2 is composed of strong positive fluxes in July and August, while negative fluxes dominate during the rest of the year. With 6.8 W/m**2, the latent heat flux more or less compensates the sensible heat flux in the annual average. Strong evaporation occurs during the snow melt period and particularly during the snow-free period in summer and fall. When the ground is covered by snow, latent heat fluxes through sublimation of snow are recorded, but are insignificant for the average surface energy budget. The near-surface atmospheric stratification is found to be predominantly unstable to neutral, when the ground is snow-free, and stable to neutral for snow-covered ground. Due to long-lasting near-surface inversions in winter, an average temperature difference of approximately 3 K exists between the air temperature at 10 m height and the surface temperature of the snow.

Late Quaternary siliciclastic/carbonate sedimentation in the Cabricorn Channel

A model is presented for hemipelagic siliciclastic and carbonate sedimentation during the last glacial-interglacial cycle in the Capricorn Channel, southern Great Barrier Reef (GBR). Stable isotope ratios, grainsize, carbonate content and mineralogy were analysed for seven cores in a depth transect from 166 to 2892 m below sea level (mbsl). Results show variations in the flux of terrigenous, neritic and pelagic sediments to the continental slope over the last sea level cycle. During the glacial lowstand terrigenous sediment influenced all the cores down to 2000 mbsl. The percentages of quartz and feldspar in the cores decreased with water depth, while the percentage of clay increased. X-ray diffraction analysis of the glacial lowstand clay mineralogy suggests that the siliciclastic sediment was primarily sourced from the Fitzroy River, which debouched directly into the northwest sector of the Capricorn Channel at this time. The cores also show a decrease in pelagic calcite and an increase in aragonite and high magnesium calcite (HMC) during the glacial. The influx of HMC and aragonite is most likely from reworking of coral reefs exposed on the continental shelf during the glacial, and also from HMC ooids precipitated at the head of the Capricorn Channel at this time. Mass accumulation rates (MARs) are high (13.5 g/cm**/kyr) during the glacial and peak at ~20 g/cm** 3/kyr in the early transgression (16-14 ka BP). MARs then decline with further sea level rise as the Fitzroy River mouth retreats from the edge of the continental shelf after 13.5 ka BP. MARs remain low (4 g/cm**3/kyr) throughout the Holocene highstand. Data for the Holocene highstand indicate there is a reduction in siliciclastic influx to the Capricorn Channel with little quartz and feldspar below 350 mbsl. However, fine-grained fluvial sediments, presumably from the Fitzroy River, were still accumulating on the mid slope down to 2000 mbsl. The proportion of pelagic calcite in the core tops increases with water depth, while HMC decreases, and is present only in trace amounts in cores below 1500 mbsl. The difference in the percentage of HMC in the deeper cores between the glacial and Holocene may reflect differences in supply or deepening of the HMC lysocline during the glacial. Sediment accumulation rates also vary between cores in the Capricorn Channel and do not show the expected exponential decrease with depth. This may be due to intermediate or deep water currents reworking the sediments. It is also possible that present bathymetry data are too sparse to detect the potential role that submarine channels may play in the distribution and accumulation of sediments. Comparison of the Capricorn Channel MARs with those for other mixed carbonate/siliciclastic provinces from the northeast margin of Australia indicates that peak MARs in the early transgression in the Capricorn Channel precede those from the central GBR and south of Fraser Island. The difference in the timing of the carbonate and siliciclastic MAR peaks along the northeast margin is primarily related to differences in the physiography and climate of the provinces. The only common trend in the MARs from the northeast margin of Australia is the near synchronicity of the carbonate and siliciclastic MAR peaks in individual sediment cores, which supports a coeval sedimentation model.

Broadband Channel Long Delay Cluster Measurements and Analysis at 2.4GHz in Subway Tunnels

The delay caused by the reflected ray in broadband communication has a great influence on the communications in subway tunnel. This paper presents measurements taken in subway tunnels at 2.4 GHz, with 5 MHz bandwidth. According to propagation characteristics of tunnel, the measurements were carried out with a frequency domain channel sounding technique, in three typical scenarios: line of sight (LOS), Non-line-of-sight (NLOS) and far line of sight (FLOS), which lead to different delay distributions. Firstly IFFT was chosen to get channel impulse response (CIR) h(t) from measured three-dimensional transfer functions. Power delay profile (PDP) was investigated to give an overview of broadband channel model. Thereafter, a long delay caused by the obturation of tunnel is observed and investigated in all the scenarios. The measurements show that the reflection can be greatly remained by the tunnel, which leads to long delay cluster where the reflection, but direct ray, makes the main contribution for radio wave propagation. Four important parameters: distribution of whole PDP power, first peak arriving time, reflection cluster duration and PDP power distribution of reflection cluster were studied to give a detailed description of long delay characteristic in tunnel. This can be used to ensure high capacity communication in tunnels

Ferromanganese nodules and micro-hardgrounds associated with the Cadiz Contourite Channel (NE Atlantic): Palaeoenvironmental records of fluid venting and bottom currents

Ferromanganese nodule fields and hardgrounds have recently been discovered in the Cadiz Contourite Channel in the Gulf of Cadiz (850–1000 m). This channel is part of a large contourite depositional system generated by the Mediterranean Outflow Water. Ferromanganese deposits linked to contourites are interesting tools for palaeoenviromental studies and show an increasing economic interest as potential mineral resources for base and strategic metals. We present a complete characterisation of these deposits based on submarine photographs and geophysical, petrographic, mineralogical and geochemical data. The genesis and growth of ferromanganese deposits, strongly enriched in Fe vs. Mn (av. 39% vs. 6%) in this contourite depositional system result from the combination of hydrogenetic and diagenetic processes. The interaction of the Mediterranean Outflow Water with the continental margin has led to the formation of Late Pleistocene–Holocene ferromanganese mineral deposits, in parallel to the evolution of the contourite depositional system triggered by climatic and tectonic events. The diagenetic growth was fuelled by the anaerobic oxidation of thermogenic hydrocarbons (δ13CPDB=−20 to −37‰) and organic matter within the channel floor sediments, promoting the formation of Fe–Mn carbonate nodules. High 87Sr/86Sr isotopic values (up to 0.70993±0.00025) observed in the inner parts of nodules are related to the influence of radiogenic fluids fuelled by deep-seated fluid venting across the fault systems in the diapirs below the Cadiz Contourite Channel. Erosive action of the Mediterranean Outflow Water undercurrent could have exhumed the Fe–Mn carbonate nodules, especially in the glacial periods, when the lower core of the undercurrent was more active in the study area. The growth rate determined by 230Thexcess/232Th was 113±11 mm/Ma, supporting the hypothesis that the growth of the nodules records palaeoenvironmental changes during the last 70 ka. Ca-rich layers in the nodules could point to the interaction between the Mediterranean Outflow Water and the North Atlantic Deep Water during the Heinrich events. Siderite–rhodochrosite nodules exposed to the oxidising seabottom waters were replaced by Fe–Mn oxyhydroxides. Slow hydrogenetic growth of goethite from the seawaters is observed in the outermost parts of the exhumed nodules and hardgrounds, which show imprints of the Mediterranean Outflow Water with low 87Sr/86Sr isotopic values (down to 0.70693±0.00081). We propose a new genetic and evolutionary model for ferromanganese oxide nodules derived from ferromanganese carbonate nodules formed on continental margins above the carbonate compensation depth and dominated by hydrocarbon seepage structures and strong erosive action of bottom currents. We also compare and discuss the generation of ferromanganese deposits in the Cadiz Contourite Channel with that in other locations and suggest that our model can be applied to ferromanganiferous deposits in other contouritic systems affected by fluid venting.

Properties and applications of high electron density structures based on InN and related compounds

El objetivo principal del presente trabajo es estudiar y explotar estructuras que presentan un gas bidimensional de electrones (2DEG) basadas en compuestos nitruros con alto contenido de indio. Existen muchas preguntas abiertas, relacionadas con el nitruro de indio y sus aleaciones, algunas de las cuales se han abordado en este estudio. En particular, se han investigado temas relacionados con el análisis y la tecnología del material, tanto para el InN y heteroestructuras de InAl(Ga)N/GaN como para sus aplicaciones a dispositivos avanzados. Después de un análisis de la dependencia de las propiedades del InN con respecto a tratamientos de procesado de dispositivos (plasma y térmicos), el problema relacionado con la formación de un contacto rectificador es considerado. Concretamente, su dificultad es debida a la presencia de acumulación de electrones superficiales en la forma de un gas bidimensional de electrones, debido al pinning del nivel de Fermi. El uso de métodos electroquímicos, comparados con técnicas propias de la microelectrónica, ha ayudado para la realización de esta tarea. En particular, se ha conseguido lamodulación de la acumulación de electrones con éxito. En heteroestructuras como InAl(Ga)N/GaN, el gas bidimensional está presente en la intercara entre GaN y InAl(Ga)N, aunque no haya polarización externa (estructuras modo on). La tecnología relacionada con la fabricación de transistores de alta movilidad en modo off (E-mode) es investigada. Se utiliza un método de ataque húmedo mediante una solución de contenido alcalino, estudiando las modificaciones estructurales que sufre la barrera. En este sentido, la necesidad de un control preciso sobre el material atacado es fundamental para obtener una estructura recessed para aplicaciones a transistores, con densidad de defectos e inhomogeneidad mínimos. La dependencia de la velocidad de ataque de las propiedades de las muestras antes del tratamiento es observada y comentada. Se presentan también investigaciones relacionadas con las propiedades básicas del InN. Gracias al uso de una puerta a través de un electrolito, el desplazamiento de los picos obtenidos por espectroscopia Raman es correlacionado con una variación de la densidad de electrones superficiales. En lo que concierne la aplicación a dispositivos, debido al estado de la tecnología actual y a la calidad del material InN, todavía no apto para dispositivos, la tesis se enfoca a la aplicación de heteroestructuras de InAl(Ga)N/GaN. Gracias a las ventajas de una barrera muy fina, comparada con la tecnología de AlGaN/GaN, el uso de esta estructura es adecuado para aplicaciones que requieren una elevada sensibilidad, estando el canal 2DEG más cerca de la superficie. De hecho, la sensibilidad obtenida en sensores de pH es comparable al estado del arte en términos de variaciones de potencial superficial, y, debido al poco espesor de la barrera, la variación de la corriente con el pH puede ser medida sin necesidad de un electrodo de referencia externo. Además, estructuras fotoconductivas basadas en un gas bidimensional presentan alta ganancia debida al elevado campo eléctrico en la intercara, que induce una elevada fuerza de separación entre hueco y electrón generados por absorción de luz. El uso de metalizaciones de tipo Schottky (fotodiodos Schottky y metal-semiconductormetal) reduce la corriente de oscuridad, en comparación con los fotoconductores. Además, la barrera delgada aumenta la eficiencia de extracción de los portadores. En consecuencia, se obtiene ganancia en todos los dispositivos analizados basados en heteroestructuras de InAl(Ga)N/GaN. Aunque presentando fotoconductividad persistente (PPC), los dispositivos resultan más rápidos con respeto a los valores que se dan en la literatura acerca de PPC en sistemas fotoconductivos. ABSTRACT The main objective of the present work is to study and exploit the two-dimensionalelectron- gas (2DEG) structures based on In-related nitride compounds. Many open questions are analyzed. In particular, technology and material-related topics are the focus of interest regarding both InNmaterial and InAl(Ga)N/GaNheterostructures (HSs) as well as their application to advanced devices. After the analysis of the dependence of InN properties on processing treatments (plasma-based and thermal), the problemof electrical blocking behaviour is taken into consideration. In particular its difficulty is due to the presence of a surface electron accumulation (SEA) in the form of a 2DEG, due to Fermi level pinning. The use of electrochemical methods, compared to standard microelectronic techniques, helped in the successful realization of this task. In particular, reversible modulation of SEA is accomplished. In heterostructures such as InAl(Ga)N/GaN, the 2DEGis present at the interface between GaN and InAl(Ga)N even without an external bias (normally-on structures). The technology related to the fabrication of normally off (E-mode) high-electron-mobility transistors (HEMTs) is investigated in heterostructures. An alkali-based wet-etching method is analysed, standing out the structural modifications the barrier underwent. The need of a precise control of the etched material is crucial, in this sense, to obtain a recessed structure for HEMT application with the lowest defect density and inhomogeneity. The dependence of the etch rate on the as-grown properties is observed and commented. Fundamental investigation related to InNis presented, related to the physics of this degeneratematerial. With the help of electrolyte gating (EG), the shift in Raman peaks is correlated to a variation in surface eletron density. As far as the application to device is concerned, due to the actual state of the technology and material quality of InN, not suitable for working devices yet, the focus is directed to the applications of InAl(Ga)N/GaN HSs. Due to the advantages of a very thin barrier layer, compared to standard AlGaN/GaN technology, the use of this structure is suitable for high sensitivity applications being the 2DEG channel closer to the surface. In fact, pH sensitivity obtained is comparable to the state-of-the-art in terms of surface potential variations, and, due to the ultrathin barrier, the current variation with pH can be recorded with no need of the external reference electrode. Moreover, 2DEG photoconductive structures present a high photoconductive gain duemostly to the high electric field at the interface,and hence a high separation strength of photogenerated electron and hole. The use of Schottky metallizations (Schottky photodiode and metal-semiconductor-metal) reduce the dark current, compared to photoconduction, and the thin barrier helps to increase the extraction efficiency. Gain is obtained in all the device structures investigated. The devices, even if they present persistent photoconductivity (PPC), resulted faster than the standard PPC related decay values.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

High reynolds numbers turbulent boundary layers

Esta tesis estudia las similitudes y diferencias entre los flujos turbulentos de pared de tipo externo e interno, en régimen incompresible, y a números de Reynolds moderada¬mente altos. Para ello consideramos tanto simulaciones numéricas como experimentos de capas límites con gradiente de presiones nulo y de flujos de canal, ambos a números de Reynolds en el rango δ+ ~ 500 - 2000. Estos flujos de cortadura son objeto de numerosas investigaciones debido a la gran importancia que tienen tanto a nivel tecnológico como a nivel de física fundamental. No obstante, todavía existen muchos interrogantes sobre aspectos básicos tales como la universalidad de los perfiles medios y de fluctuación de las velocidades o de la presión, tanto en la zona cercana a la pared como en la zona logarítmica, el escalado y el efecto del número de Reynolds, o las diferencias entre los flujos internos y externos en la zona exterior. En éste estudio hemos utilizado simulaciones numéricas ya existentes de canales y capas límites a números de Reynolds δ+ ~ 2000 y δ+ ~ 700, respectivamente. Para poder comparar ambos flujos a igual número de Reynolds hemos realizado una nueva simulación directa de capa límite en el rango δ+ ~ 1000-2000. Los resultados de la misma son presentados y analizados en detalle. Los datos sin postprocesar y las estadísticas ya postprocesadas están públicamente disponibles en nuestro sitio web.162 El análisis de las estadísticas usando un único punto confirma la existencia de perfiles logarítmicos para las fluctuaciones de la velocidad transversal w'2+ y de la presión p'2+ en ambos tipos de flujos, pero no para la velocidad normal v'2+ o la velocidad longitudinal u'2+. Para aceptar o rechazar la existencia de un rango logarítmico en u'2+ se requieren números de Reynolds más altos que los considerados en éste trabajo. Una de las conse¬cuencias más importantes de poseer tales perfiles es que el valor máximo de la intensidad, que se alcanza cerca de la pared, depende explícitamente del número de Reynolds. Esto ha sido confirmado tras analizar un gran número de datos experimentales y numéricos, cor¬roborando que el máximo de u'2+, p/2+, y w'2+ aumenta proporcionalmente con el log(δ+). Por otro lado, éste máximo es más intenso en los flujos externos que en los internos. La máxima diferencia ocurre en torno a y/δ ~ 0.3-0.5, siendo esta altura prácticamente independiente del número de Reynolds considerado. Estas diferencias se originan como consecuencia del carácter intermitente de las capas límites, que es inexistente en los flujos internos. La estructura de las fluctuaciones de velocidad y de presión, junto con la de los esfuer¬zos de Reynolds, se han investigado por medio de correlaciones espaciales tridimensionales considerando dos puntos de medida. Hemos obtenido que el tamaño de las mismas es gen¬eralmente mayor en canales que en capas límites, especialmente en el caso de la correlación longitudinal Cuu en la dirección del flujo. Para esta correlación se demuestra que las es¬tructuras débilmente correladas presentan longitudes de hasta 0(75), en el caso de capas límites, y de hasta 0(185) en el caso de canales. Estas longitudes se obtienen respecti-vamente en la zona logarítmica y en la zona exterior. Las longitudes correspondientes en la dirección transversal son significativamente menores en ambos flujos, 0(5 — 25). La organización espacial de las correlaciones es compatible con la de una pareja de rollos casi paralelos con dimensiones que escalan en unidades exteriores. Esta organización se mantiene al menos hasta y ~ 0.65, altura a la cual las capas límites comienzan a organi¬zarse en rollos transversales. Este comportamiento es sin embargo más débil en canales, pudiéndose observar parcialmente a partir de y ~ 0.85. Para estudiar si estas estructuras están onduladas a lo largo de la dirección transver¬sal, hemos calculado las correlaciones condicionadas a eventos intensos de la velocidad transversal w'. Estas correlaciones revelan que la ondulación de la velocidad longitudinal aumenta conforme nos alejamos de la pared, sugiriendo que las estructuras están más alineadas en la zona cercana a la pared que en la zona lejana a ella. El por qué de esta ondulación se encuentra posiblemente en la configuración a lo largo de diagonales que presenta w'. Estas estructuras no sólo están onduladas, sino que también están inclinadas respecto a la pared con ángulos que dependen de la variable considerada, de la altura, y de el contorno de correlación seleccionado. Por encima de la zona tampón e independien¬temente del número de Reynolds y tipo de flujo, Cuu presenta una inclinación máxima de unos 10°, las correlaciones Cvv y Cm son esencialmente verticales, y Cww está inclinada a unos 35°. Summary This thesis studies the similitudes and differences between external and internal in¬compressible wall-bounded turbulent flows at moderately-high Reynolds numbers. We consider numerical and experimental zero-pressure-gradient boundary layers and chan¬nels in the range of δ+ ~ 500 — 2000. These shear flows are subjects of intensive research because of their technological importance and fundamental physical interest. However, there are still open questions regarding basic aspects such as the universality of the mean and fluctuating velocity and pressure profiles at the near-wall and logarithmic regions, their scaling and the effect of the Reynolds numbers, or the differences between internal and external flows at the outer layer, to name but a few. For this study, we made use of available direct numerical simulations of channel and boundary layers reaching δ+ ~ 2000 and δ+ ~ 700, respectively. To fill the gap in the Reynolds number, a new boundary layer simulation in the range δ+ ~ 1000-2000 is presented and discussed. The original raw data and the post-processed statistics are publicly available on our website.162 The analysis of the one-point statistic confirms the existence of logarithmic profiles for the spanwise w'2+ and pressure p'2+ fluctuations for both type of flows, but not for the wall-normal v'2+ or the streamwise u'2+ velocities. To accept or reject the existence of a logarithmic range in u'2+ requires higher Reynolds numbers than the ones considered in this work. An important consequence of having such profiles is that the maximum value of the intensities, reached near the wall, depends on the Reynolds number. This was confirmed after surveying a wide number of experimental and numerical datasets, corrob¬orating that the maximum of ul2+, p'2+, and w'2+ increases proportionally to log(δ+). On the other hand, that maximum is more intense in external flows than in internal ones, differing the most around y/δ ~ 0.3-0.5, and essentially independent of the Reynolds number. We discuss that those differences are originated as a consequence of the inter¬mittent character of boundary layers that is absent in internal flows. The structure of the velocity and pressure fluctuations, together with those of the Reynolds shear stress, were investigated using three-dimensional two-point spatial correlations. We find that the correlations extend over longer distances in channels than in boundary layers, especially in the case of the streamwise correlation Cuu in the flow direc-tion. For weakly correlated structures, the maximum streamwise length of Cuu is O(78) for boundary layers and O(188) for channels, attained at the logarithmic and outer regions respectively. The corresponding lengths for the transverse velocities and for the pressure are shorter, 0(8 — 28), and of the same order for both flows. The spatial organization of the velocity correlations is shown to be consistent with a pair of quasi-streamwise rollers that scales in outer units. That organization is observed until y ~ 0.68, from which boundary layers start to organize into spanwise rollers. This effect is weaker in channels, and it appears at y ~ 0.88. We present correlations conditioned to intense events of the transversal velocity, w', to study if these structures meander along the spanwise direction. The results indicate that the streamwise velocity streaks increase their meandering proportionally to the distance to the wall, suggesting that the structures are more aligned close to the wall than far from it. The reason behind this meandering is probably due to the characteristic organization along diagonals of w'. These structures not only meander along the spanwise direction, but they are also inclined to the wall at angles that depend on the distance from the wall, on the variable being considered, and on the correlation level used to define them. Above the buffer layer and independent of the Reynolds numbers and type of flow, the maximum inclination of Cuu is about 10°, Cvv and Cpp are roughly vertical, and Cww is inclined by 35°.