High-precision digital lock-in measurements of critical current and AC loss in HTS 2G-Tapes

Application of High Temperature Superconducting (HTS) has been increasingly popular since the new superconducting materials were discovered. This paper presents a new high-precision digital lock-in measurement technique which is used for measuring critical current and AC loss of the 2nd Generation HTS tape. Using a lock-in amplifier and nano-voltage meter, we can resolve signals at nano-volt level, while using a specially designed compensation coil we can cancel out inductive by adjusting the coil inductance. Furthermore, a finer correction for the inductive component can be achieved by adjusting the reference phase of the lock-in amplifier. The critical current and AC loss measurement algorithms and hardware layout are described and analyzed, and results for both numerical and experimental data under varieties of frequencies are presented. © 2008 SICE.

A crowding model of visual clutter.

Visual information is difficult to search and interpret when the density of the displayed information is high or the layout is chaotic. Visual information that exhibits such properties is generally referred to as being "cluttered." Clutter should be avoided in information visualizations and interface design in general because it can severely degrade task performance. Although previous studies have identified computable correlates of clutter (such as local feature variance and edge density), understanding of why humans perceive some scenes as being more cluttered than others remains limited. Here, we explore an account of clutter that is inspired by findings from visual perception studies. Specifically, we test the hypothesis that the so-called "crowding" phenomenon is an important constituent of clutter. We constructed an algorithm to predict visual clutter in arbitrary images by estimating the perceptual impairment due to crowding. After verifying that this model can reproduce crowding data we tested whether it can also predict clutter. We found that its predictions correlate well with both subjective clutter assessments and search performance in cluttered scenes. These results suggest that crowding and clutter may indeed be closely related concepts and suggest avenues for further research.

Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.

Beyond 2D-grids: A dependence maximization view on image browsing

Ideally, one would like to perform image search using an intuitive and friendly approach. Many existing image search engines, however, present users with sets of images arranged in some default order on the screen, typically the relevance to a query, only. While this certainly has its advantages, arguably, a more flexible and intuitive way would be to sort images into arbitrary structures such as grids, hierarchies, or spheres so that images that are visually or semantically alike are placed together. This paper focuses on designing such a navigation system for image browsers. This is a challenging task because arbitrary layout structure makes it difficult - if not impossible - to compute cross-similarities between images and structure coordinates, the main ingredient of traditional layouting approaches. For this reason, we resort to a recently developed machine learning technique: kernelized sorting. It is a general technique for matching pairs of objects from different domains without requiring cross-domain similarity measures and hence elegantly allows sorting images into arbitrary structures. Moreover, we extend it so that some images can be preselected for instance forming the tip of the hierarchy allowing to subsequently navigate through the search results in the lower levels in an intuitive way. Copyright 2010 ACM.

Multi-objective optimisation of horizontal axis wind turbine structure and energy production using aerofoil and blade properties as design variables

The design of wind turbine blades is a true multi-objective engineering task. The aerodynamic effectiveness of the turbine needs to be balanced with the system loads introduced by the rotor. Moreover the problem is not dependent on a single geometric property, but besides other parameters on a combination of aerofoil family and various blade functions. The aim of this paper is therefore to present a tool which can help designers to get a deeper insight into the complexity of the design space and to find a blade design which is likely to have a low cost of energy. For the research we use a Computational Blade Optimisation and Load Deflation Tool (CoBOLDT) to investigate the three extreme point designs obtained from a multi-objective optimisation of turbine thrust, annual energy production as well as mass for a horizontal axis wind turbine blade. The optimisation algorithm utilised is based on Multi-Objective Tabu Search which constitutes the core of CoBOLDT. The methodology is capable to parametrise the spanning aerofoils with two-dimensional Free Form Deformation and blade functions with two tangentially connected cubic splines. After geometry generation we use a panel code to create aerofoil polars and a stationary Blade Element Momentum code to evaluate turbine performance. Finally, the obtained loads are fed into a structural layout module to estimate the mass and stiffness of the current blade by means of a fully stressed design. For the presented test case we chose post optimisation analysis with parallel coordinates to reveal geometrical features of the extreme point designs and to select a compromise design from the Pareto set. The research revealed that a blade with a feasible laminate layout can be obtained, that can increase the energy capture and lower steady state systems loads. The reduced aerofoil camber and an increased L/. D-ratio could be identified as the main drivers. This statement could not be made with other tools of the research community before. © 2013 Elsevier Ltd.

Isolating shallow foundations from seismic loading

Most modern design codes do not allow for movement between a shallow foundation and the underlying soil during seismic loading. Consequently, the full magnitude of seismic energy is transmitted from the soil to the foundation during an earthquake. This energy either has to be dissipated before reaching the superstructure via engineering solutions such as base isolation systems, or the structure itself must withstand the full impact of the earthquake resulting in high material usage and expensive design. However, the inherent hysteric behaviour of soil can be used to isolate a foundation from the underlying soil. As part of a study into the soil-structure-interaction of shallow foundations, methods to optimise foundation isolation were investigated. In this paper the results from centrifuge tests investigating two of these methods are compared to results when no special foundation layout was implemented and the impact of the proposed isolation methods is discussed. © 2010 Taylor & Francis Group, London.

Optimising the dynamic performance of an all-wide-bandgap cascode switch

A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.

A 40 Gb/s optical bus for optical backplane interconnections

Optical technologies have received large interest in recent years for use in board-level interconnects. Polymer multimode waveguides in particular, constitute a promising technology for high-capacity optical backplanes as they can be cost-effectively integrated onto conventional printed circuit boards (PCBs). This paper presents the first optical backplane demonstrator based on the use of PCB-integrated polymer multimode waveguides and a regenerative shared bus architecture. The backplane demonstrator is formed with commercially-available low-cost electronic and photonic components onto conventional FR4 substrates and comprises two opto-electronic (OE) bus modules interconnected via a prototype regenerator unit. The system enables interconnection between the connected cards over four optical channels, each operating at 10 Gb/s. Bus extension is achieved by cascading OE bus modules via 3R regenerator units, overcoming therefore the inherent limitation of optical bus topologies in the maximum number of cards that can be connected to the bus. Details of the design, fabrication, and assembly of the different parts of this optical bus backplane are presented and related optical and data transmission characterisation studies are reported. The optical layer of the OE bus modules comprises a four-channel three-card waveguide layout that is compatible with VCSEL/PD arrays and ribbon fibres. All on-board optical paths exhibit insertion losses below 13 dB and intra-channel crosstalk lower than -29 dB. The robustness of the signal distribution from the bus inputs to all respective bus output ports in the presence of input misalignment is demonstrated, while 1 dB input alignment tolerances of approximately ±10 μm are obtained. The electrical layer of the OE bus modules comprises the essential driving circuitry for 1×4 VCSEL and PD arrays and the corresponding control and power regulation circuits. The interface between the optical and electrical layers of the bus modules is achieved with simple OE connectors that enable end-fired optical coupling into and out of the on-board polymer waveguides. The backplane demonstrator achieves error-free (BER < 10-12) 10 Gb/s data transmission over each optical channel, enabling therefore, an aggregate interconnection capacity of 40 Gb/s between any connected cards. © 1983-2012 IEEE.

GPU-accelerated optimization of fuel treatments for mitigating wildfire hazard

Fuel treatment is considered a suitable way to mitigate the hazard related to potential wildfires on a landscape. However, designing an optimal spatial layout of treatment units represents a difficult optimization problem. In fact, budget constraints, the probabilistic nature of fire spread and interactions among the different area units composing the whole treatment, give rise to challenging search spaces on typical landscapes. In this paper we formulate such optimization problem with the objective of minimizing the extension of land characterized by high fire hazard. Then, we propose a computational approach that leads to a spatially-optimized treatment layout exploiting Tabu Search and General-Purpose computing on Graphics Processing Units (GPGPU). Using an application example, we also show that the proposed methodology can provide high-quality design solutions in low computing time. © 2013 The Authors. Published by Elsevier B.V.

Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given. © 2014 Elsevier Ltd. All rights reserved.

The next-generation sequencing technology: A technology review and future perspective

As one of the most powerful tools in biomedical research, DNA sequencing not only has been improving its productivity in an exponential growth rate but also been evolving into a new layout of technological territories toward engineering and physical disciplines over the past three decades. In this technical review, we look into technical characteristics of the next-gen sequencers and provide prospective insights into their future development and applications. We envisage that some of the emerging platforms are capable of supporting the $1000 genome and $100 genome goals if given a few years for technical maturation. We also suggest that scientists from China should play an active role in this campaign that will have profound impact on both scientific research and societal healthcare systems.

Influence of heated catalyzer on thermal distribution of substrate in HWCVD system

Based on Stefan-Boltzman and Lambert theorems, the radiation energy distribution on substrate (REDS) from catalyzer with parallel filament geometry has been simulated by variation of filament and system layout in hot-wire chemical vapor deposition. The REDS uniformity is sensitive to the distance between filament and substrate d(f-s) when d(f-s) less than or equal to 4 cm. As d(f-s) > 4 cm, the REDS uniformity is independent of d(f-s) and is mainly determined by filament number and filament separation. Two-dimensional calculation shows that the REDS uniformity is limited by temperature decay at filament edges. The simulation data are in good agreement with experiments. (C) 2003 Elsevier Science B.V. All rights reserved.

A Low Power Baseband Chain for CMMB Application

This paper presents experimental results of an analog baseband circuit for China Multimedia Mobile Broadcasting (CMMB) direct conversion receiver in 0.35um SiGe BiCMOS process. It is the first baseband of CMMB RFIC reported so far. A 8(th)-order chebyshev low pass filter (LPF) with calibration system is used in the analog baseband circuit, the filter provides 0.5 dB passband ripple and -35 dB attenuation at 6MHz with the cutoff frequency at 4MHz, the calibration of filter is reported to achieve the bandwidth accuracy of 3%. The baseband variable gain amplifier (VGA) achieves more than 40 dB gain tuning with temperature compensation. In addition, A DC offset cancellation circuit is also introduced to remove the offset from layout and self-mixing, and the remaining offset voltage and current consumption are only 6mV and 412uA respectively. Implemented in a 0.35um SiGe technology with 1.1 mm(2) die size, this tuner baseband achieves OIP3 of 25.5 dBm and dissipate 16.4 mA under 2.8-V supply.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

面向ETL过程的数据质量控制系统的设计与实现

ETL过程是一个从分布数据源(包括数据库、应用系统、文件系统等)抽取数据，进行转换、集成和传输，并最终加载到目标系统的过程。传统的ETL过程主要服务于数据仓库(Data Warehouse)，属于企业决策支持系统的一部分。随着数据集成技术的发展和轻量级的数据集成中间件的出现，ETL过程广泛应用于企业数据集成与数据交换系统。在ETL过程中，数据质量控制是一个极为重要的基本组件和功能，它对集成中的数据进行检测、转换、清洗，以防止“脏”数据进入目标系统。在ETL过程中如果缺少对数据质量的有效控制，就会导致数据集成项目无法圆满实现目标或彻底失败。 针对ETL过程中存在的数据质量问题，设计并实现面向ETL过程的数据质量控制系统，是本文研究的重点。论文通过对ETL过程中各阶段可能产生的数据质量问题进行了分类，并对质量控制需求建模，提出一个面向ETL过程的数据质量控制框架，该框架通过对源端数据的分析来指导ETL的设计，通过灵活、可配置、可扩展的数据处理机制实现数据的过滤、转换与清洗，并支持对数据质量处理全过程进行监控。在该框架基础上，论文特别在灵活的数据处理机制、数据分析、数据过滤和数据清洗四个方面进行了探讨。在数据处理机制方面，提出了基于插件元模型的数据处理机制，该机制可以满足用户对数据过滤、数据转换与数据清洗等功能的各种定制需求，并具有较强的可扩展性；在数据分析方面，根据字段类型对数据进行分类统计，并针对大数据量统计分析问题，提出了可自动配置的不同数据统计策略；在数据过滤方面，通过将抽取数据的SQL语句重写的方式，过滤不满足完整性约束的元组；在数据清洗方法方面给出了一种利用统计信息动态确定属性相似度权重的方法，对基于字段的相似记录检测算法的领域无关算法进行了改进，提高了数据检测的准确性。在上述工作基础上，在数据集成中间件OnceDI中设计并实现了数据质量控制系统，并在设计中通过设计模式的应用增强系统的可扩展性。