Accelerated apoptosis of lymphocytes by augmented induction of Bax in SSI-1 (STAT-induced STAT inhibitor-1) deficient mice

Growth, differentiation, and programmed cell death (apoptosis) are mainly controlled by cytokines. The Janus kinase–signal transducers and activators of transcription (JAK-STAT) signal pathway is an important component of cytokine signaling. We have previously shown that STAT3 induces a molecule designated as SSI-1, which inhibits STAT3 functions. To clarify the physiological roles of SSI-1 in vivo, we generated, here, mice lacking SSI-1. These SSI-1−/− mice displayed growth retardation and died within 3 weeks after birth. Lymphocytes in the thymus and spleen of the SSI-1−/− mice exhibited accelerated apoptosis with aging, and their number was 20–25% of that in SSI-1+/+ mice at 10 days of age. However, the differentiation of lymphocytes lacking SSI-1 appeared to be normal. Among various pro- and anti-apoptotic molecules examined, an up-regulation of Bax was found in lymphocytes of the spleen and thymus of SSI-1−/− mice. These findings suggest that SSI-1 prevents apoptosis by inhibiting the expression of Bax.

Accelerated evolution and Muller's rachet in endosymbiotic bacteria.

Many bacteria live only within animal cells and infect hosts through cytoplasmic inheritance. These endosymbiotic lineages show distinctive population structure, with small population size and effectively no recombination. As a result, endosymbionts are expected to accumulate mildly deleterious mutations. If these constitute a substantial proportion of new mutations, endosymbionts will show (i) faster sequence evolution and (ii) a possible shift in base composition reflecting mutational bias. Analyses of 16S rDNA of five independently derived endosymbiont clades show, in every case, faster evolution in endosymbionts than in free-living relatives. For aphid endosymbionts (genus Buchnera), coding genes exhibit accelerated evolution and unusually low ratios of synonymous to nonsynonymous substitutions compared to ratios for the same genes for enterics. This concentration of the rate increase in nonsynonymous substitutions is expected under the hypothesis of increased fixation of deleterious mutations. Polypeptides for all Buchnera genes analyzed have accumulated amino acids with codon families rich in A+T, supporting the hypothesis that substitutions are deleterious in terms of polypeptide function. These observations are best explained as the result of Muller's ratchet within small asexual populations, combined with mutational bias. In light of this explanation, two observations reported earlier for Buchnera, the apparent loss of a repair gene and the overproduction of a chaperonin, may reflect compensatory evolution. An alternative hypothesis, involving selection on genomic base composition, is contradicted by the observation that the speedup is concentrated at nonsynonymous sites.

Enhanced and accelerated lymphoproliferation in Fas-null mice.

Fas is a 45-kDa membrane protein that transduces an apoptotic signal. The mouse lymphoproliferation (lpr) mutation is a leaky mutation of Fas. In this study, we examined lymphocyte development in Fas-null mice generated by gene targeting. The Fas-/- mice progressively accumulated abnormal T cells (Thy1+, B220+, CD4-, and CD8-) and developed lymphadenopathy and splenomegaly, which were much more accelerated and pronounced than those in lpr mice. In addition, the Fas-null mice showed lymphocytosis, accompanied by lymphocytic infiltration in the lungs and liver. The number of apparently normal B cells also increased, and large amounts of immunoglobulins, including anti-DNA antibodies, were produced. Thymic clonal deletion, assessed by deletion of T cells reactive to mouse endogenous superantigens, was apparently normal in the Fas-/- mice, whereas the peripheral clonal deletion of mature T cells against a bacterial superantigen was impaired. These results suggested that Fas plays a decisive role in peripheral clonal deletion but not in negative selection in the thymus.

Accelerated induction of experimental allergic encephalomyelitis in PL/J mice by a non-V beta 8-specific superantigen.

Superantigens such as the staphylococcal enterotoxins can play an important role in exacerbation of autoimmune disorders such as experimental allergic encephalomyelitis (EAE) in mice. In fact, superantigens can reactivate EAE in PL/J mice that have been sensitized to rat myelin basic protein (MBP). The T-cell subset predominantly responsible for disease in PL/J mice bears the V beta 8+ T-cell antigen receptor (TCR). The question arises as to whether T cells bearing other V beta specificities are involved in induction or reactivation of EAE with superantigen. Thus, we have investigated the ability of a non-V beta 8-specific superantigen, staphylococcal enterotoxin A (SEA) (V beta specificities 1, 3, 10, 11, and 17), to induce EAE in PL/J mice that have been previously protected from disease by anergy and deletion of V beta 8+ T cells. PL/J mice were first pretreated with the V beta 8-specific superantigen staphylococcal enterotoxin B (SEB) and then immunized with MBP. These mice exhibited V beta 8-specific anergy and depletion and did not develop EAE, even when further treated with SEB. However, administration of SEA to these same mice induced an initial episode of EAE which was characterized by severe hindleg paralysis and accelerated onset of disease. In contrast to SEB pretreatment, PL/J mice pretreated with SEA did develop EAE when immunized with MBP, and after resolution of clinical signs of disease these mice were susceptible to relapse of EAE induced by SEB but not by SEA. Thus, superantigens can activate encephalitogenic MBP-specific non-V beta 8+ T cells to cause EAE in PL/J mice. These data suggest that superantigens can play a central role in autoimmune disorders and that they introduce a profound complexity to autoimmune diseases such as EAE, akin to the complexity seen in multiple sclerosis.

Accelerated evolution in the protein-coding regions is universal in crotalinae snake venom gland phospholipase A2 isozyme genes.

The nucleotide sequences of four genes encoding Trimeresurus gramineus (green habu snake, crotalinae) venom gland phospholipase A2 (PLA2; phosphatidylcholine 2-acylhydrolase, EC 3.1.1.4) isozymes were compared internally and externally with those of six genes encoding Trimeresurus flavoviridis (habu snake, crotalinae) venom gland PLA2 isozymes. The numbers of nucleotide substitutions per site (KN) for the noncoding regions including introns were one-third to one-eighth of the numbers of nucleotide substitutions per synonymous site (KS) for the protein-coding regions of exons, indicating that the noncoding regions are much more conserved than the protein-coding regions. The KN values for the introns were found to be nearly equivalent to those of introns of T. gramineus and T. flavoviridis TATA box-binding protein genes, which are assumed to be a general (nonvenomous) gene. Thus, it is evident that the introns of venom gland PLA2 isozyme genes have evolved at a similar rate to those of nonvenomous genes. The numbers of nucleotide substitutions per nonsynonymous site (KA) were close to or larger than the KS values for the protein-coding regions in venom gland PLA2 isozyme genes. All of the data combined reveal that Darwinian-type accelerated evolution has universally occurred only in the protein-coding regions of crotalinae snake venom PLA2 isozyme genes.

Interfaz software/hardware entre Raspberry Pi y FPGA Spartan-6 y su aplicación a simulación dirigida por eventos

Hoy día vivimos en la sociedad de la tecnología, en la que la mayoría de las cosas cuentan con uno o varios procesadores y es necesario realizar cómputos para hacer más agradable la vida del ser humano. Esta necesidad nos ha brindado la posibilidad de asistir en la historia a un acontecimiento sin precedentes, en el que la cantidad de transistores era duplicada cada dos años, y con ello, mejorada la velocidad de cómputo (Moore, 1965). Tal acontecimiento nos ha llevado a la situación actual, en la que encontramos placas con la capacidad de los computadores de hace años, consumiendo muchísima menos energía y ocupando muchísimo menos espacio, aunque tales prestaciones quedan un poco escasas para lo que se requiere hoy día. De ahí surge la idea de comunicar placas que se complementan en aspectos en las que ambas se ven limitadas. En nuestro proyecto desarrollaremos una interfaz s oftware/hardware para facilitar la comunicación entre dos placas con distintas prestaciones, a saber, una Raspberry Pi modelo A 2012 y una FPGA Spartan XSA3S1000 con placa extendida XStend Board V3.0. Dicha comunicación se basará en el envío y recepción de bits en serie, y será la Raspberry Pi quien marque las fases de la comunicación. El proyecto se divide en dos partes: La primera parte consiste en el desarrollo de un módulo para el kernel de Linux, que se encarga de gestionar las entradas y salidas de datos de la Raspberry Pi cuando se realizan las pertinentes llamadas de write o read. Mediante el control de los GPIO y la gestión de las distintas señales, se realiza la primera fase de la comunicación. La segunda parte consiste en el desarrollo de un diseño en VHDL para la FPGA, mediante el cual se pueda gestionar la recepción, cómputo y posterior envío de bits, de forma que la Raspberry Pi pueda disponer de los datos una vez hayan sido calculados. Ambas partes han sido desarrolladas bajo licencias libres (GPL) para que estén disponibles a cualquier persona interesada en el desarrollo y que deseen su reutilización.

Herramienta de gestión de contadores hardware para Android

PMCTrack es una herramienta de código abierto para Linux que permite monitorizar el rendimiento de las aplicaciones haciendo uso de los contadores hardware del procesador. Esta herramienta soporta la captura de métricas como el número de instrucciones por ciclo o la tasa de fallos de cache. El objetivo de este proyecto es portar PMCTrack al sistema operativo Android sobre plataformas que integran procesadores de ARM. Esto conlleva la realización de las siguientes tareas: (1) modificación de la variante del kernel Linux propia de Android para incluir las extensiones requeridas por el módulo del kernel de PMCTrack, (2) adaptación de las herramientas de modo usuario de PMCTrack, y (3) desarrollo de una aplicación Android que permita visualizar en tiempo real las medidas de los contadores recabadas para las distintas aplicaciones que están siendo monitorizadas. Para poner a prueba la adaptación de la herramienta PMCTrack al sistema operativo Android y mostrar la utilidad de nuestras aportaciones, se han llevado a cabo diversos casos de estudio empleando la placa de desarrollo Odroid XU4.

Practical experiences on a real pumping system emulated by a hardware model and used as a remote laboratory

Paper submitted to ACE 2013, 10th IFAC Symposium on Advances in Control Education, University of Sheffield, UK, August 28-30, 2013.

An application of fuzzy logic for hardware/software partitioning in embedded systems

Hardware/Software partitioning (HSP) is a key task for embedded system co-design. The main goal of this task is to decide which components of an application are to be executed in a general purpose processor (software) and which ones, on a specific hardware, taking into account a set of restrictions expressed by metrics. In last years, several approaches have been proposed for solving the HSP problem, directed by metaheuristic algorithms. However, due to diversity of models and metrics used, the choice of the best suited algorithm is an open problem yet. This article presents the results of applying a fuzzy approach to the HSP problem. This approach is more flexible than many others due to the fact that it is possible to accept quite good solutions or to reject other ones which do not seem good. In this work we compare six metaheuristic algorithms: Random Search, Tabu Search, Simulated Annealing, Hill Climbing, Genetic Algorithm and Evolutionary Strategy. The presented model is aimed to simultaneously minimize the hardware area and the execution time. The obtained results show that Restart Hill Climbing is the best performing algorithm in most cases.

Algoritmos metaheurísticos en el problema del particionado hardware/software de sistemas embebidos

El particionado hardware/software es una tarea fundamental en el co-diseño de sistemas embebidos. En ella se decide, teniendo en cuenta las métricas de diseño, qué componentes se ejecutarán en un procesador de propósito general (software) y cuáles en un hardware específico. En los últimos años se han propuesto diversas soluciones al problema del particionado dirigidas por algoritmos metaheurísticos. Sin embargo, debido a la diversidad de modelos y métricas utilizadas, la elección del algoritmo más apropiado sigue siendo un problema abierto. En este trabajo se presenta una comparación de seis algoritmos metaheurísticos: Búsqueda aleatoria (Random search), Búsqueda tabú (Tabu search), Recocido simulado (Simulated annealing), Escalador de colinas estocástico (Stochastic hill climbing), Algoritmo genético (Genetic algorithm) y Estrategia evolutiva (Evolution strategy). El modelo utilizado en la comparación está dirigido a minimizar el área ocupada y el tiempo de ejecución, las restricciones del modelo son consideradas como penalizaciones para incluir en el espacio de búsqueda otras soluciones. Los resultados muestran que los algoritmos Escalador de colinas estocástico y Estrategia evolutiva son los que mejores resultados obtienen en general, seguidos por el Algoritmo genético.

Real-time 3D semi-local surface patch extraction using GPGPU

Feature vectors can be anything from simple surface normals to more complex feature descriptors. Feature extraction is important to solve various computer vision problems: e.g. registration, object recognition and scene understanding. Most of these techniques cannot be computed online due to their complexity and the context where they are applied. Therefore, computing these features in real-time for many points in the scene is impossible. In this work, a hardware-based implementation of 3D feature extraction and 3D object recognition is proposed to accelerate these methods and therefore the entire pipeline of RGBD based computer vision systems where such features are typically used. The use of a GPU as a general purpose processor can achieve considerable speed-ups compared with a CPU implementation. In this work, advantageous results are obtained using the GPU to accelerate the computation of a 3D descriptor based on the calculation of 3D semi-local surface patches of partial views. This allows descriptor computation at several points of a scene in real-time. Benefits of the accelerated descriptor have been demonstrated in object recognition tasks. Source code will be made publicly available as contribution to the Open Source Point Cloud Library.

Partición hardware software de un codificador JPEG utilizando escalador de colinas estocástico

La partición hardware/software es una etapa clave dentro del proceso de co-diseño de los sistemas embebidos. En esta etapa se decide qué componentes serán implementados como co-procesadores de hardware y qué componentes serán implementados en un procesador de propósito general. La decisión es tomada a partir de la exploración del espacio de diseño, evaluando un conjunto de posibles soluciones para establecer cuál de estas es la que mejor balance logra entre todas las métricas de diseño. Para explorar el espacio de soluciones, la mayoría de las propuestas, utilizan algoritmos metaheurísticos; destacándose los Algoritmos Genéticos, Recocido Simulado. Esta decisión, en muchos casos, no es tomada a partir de análisis comparativos que involucren a varios algoritmos sobre un mismo problema. En este trabajo se presenta la aplicación de los algoritmos: Escalador de Colinas Estocástico y Escalador de Colinas Estocástico con Reinicio, para resolver el problema de la partición hardware/software. Para validar el empleo de estos algoritmos se presenta la aplicación de este algoritmo sobre un caso de estudio, en particular la partición hardware/software de un codificador JPEG. En todos los experimentos es posible apreciar que ambos algoritmos alcanzan soluciones comparables con las obtenidas por los algoritmos utilizados con más frecuencia.

3D model reconstruction using neural gas accelerated on GPU

In this work, we propose the use of the neural gas (NG), a neural network that uses an unsupervised Competitive Hebbian Learning (CHL) rule, to develop a reverse engineering process. This is a simple and accurate method to reconstruct objects from point clouds obtained from multiple overlapping views using low-cost sensors. In contrast to other methods that may need several stages that include downsampling, noise filtering and many other tasks, the NG automatically obtains the 3D model of the scanned objects. To demonstrate the validity of our proposal we tested our method with several models and performed a study of the neural network parameterization computing the quality of representation and also comparing results with other neural methods like growing neural gas and Kohonen maps or classical methods like Voxel Grid. We also reconstructed models acquired by low cost sensors that can be used in virtual and augmented reality environments for redesign or manipulation purposes. Since the NG algorithm has a strong computational cost we propose its acceleration. We have redesigned and implemented the NG learning algorithm to fit it onto Graphics Processing Units using CUDA. A speed-up of 180× faster is obtained compared to the sequential CPU version.