SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

Politics, Patriotism and Women in Ireland, Britain and Colonial America, c.1700-c.1780

The use of the consumer boycott as a political tool is commonly associated with pre-revolutionary colonial America and has been identified by historians as an important means through which American women were politicized. This article argues that from the late seventeenth century, Irish political discourse advocated the non-consumption of imported goods and support for home manufactures by women in ways that were strikingly similar to those used later in North America. In Ireland and, subsequently in the American colonies, the virtuous woman consumer was given an active public role by political and social commentators. Rather than being a “brilliantly original American invention,” as T. H. Breen has argued, the political exploitation of a consumer boycott and the promotion of local industry were among what Bernard Bailyn has described as the “set of ideas, already in scattered ways familiar” to the revolutionary leaders through the Irish experience. The article also argues that a shared colonial environment gave Irish and American women a public patriotic role in the period, c. 1700–1780 that they did not have in the home countries of England and Scotland.

Techniques for multiple-set synchronous islanding control

Power system islanding can improve the continuity of power supply. Synchronous islanded operation enables the islanded system to remain in phase with the main power system while not electrically connected, so avoiding out-of-synchronism re-closure. Specific consideration is required for the multiple-set scenario. In this paper a suitable island management system is proposed, with the emphasis being on maximum island flexibility by allowing passive islanding transitions to occur, facilitated by intelligent control. These transitions include: island detection, identification, fragmentation, merging and return-to-mains. It can be challenging to detect these transitions while maintaining syn-chronous islanded operation. The performance of this control system in the presence of a variable wind power in-feed is also examined. A Mathworks SimPowerSystems simulation is used to investigate the performance of the island management system. The benefit and requirements for energy storage, com-munications and distribution system protection for this application are considered.

QR decomposition-based matrix inversion for high performance embedded MIMO receivers

Real-time matrix inversion is a key enabling technology in multiple-input multiple-output (MIMO) communications systems, such as 802.11n. To date, however, no matrix inversion implementation has been devised which supports real-time operation for these standards. In this paper, we overcome this barrier by presenting a novel matrix inversion algorithm which is ideally suited to high performance floating-point implementation. We show how the resulting architecture offers fundamentally higher performance than currently published matrix inversion approaches and we use it to create the first reported architecture capable of supporting real-time 802.11n operation. Specifically, we present a matrix inversion approach based on modified squared Givens rotations (MSGR). This is a new QR decomposition algorithm which overcomes critical limitations in other QR algorithms that prohibits their application to MIMO systems. In addition, we present a novel modification that further reduces the complexity of MSGR by almost 20%. This enables real-time implementation with negligible reduction in the accuracy of the inversion operation, or the BER of a MIMO receiver based on this.

Evaluation of Random Delay Insertion against DPA on FPGAs

Side-channel attacks (SCA) threaten electronic cryptographic devices and can be carried out by monitoring the physical characteristics of security circuits. Differential Power Analysis (DPA) is one the most widely studied side-channel attacks. Numerous countermeasure techniques, such as Random Delay Insertion (RDI), have been proposed to reduce the risk of DPA attacks against cryptographic devices. The RDI technique was first proposed for microprocessors but it was shown to be unsuccessful when implemented on smartcards as it was vulnerable to a variant of the DPA attack known as the Sliding-Window DPA attack.Previous research by the authors investigated the use of the RDI countermeasure for Field Programmable Gate Array (FPGA) based cryptographic devices. A split-RDI technique wasproposed to improve the security of the RDI countermeasure. A set of critical parameters wasalso proposed that could be utilized in the design stage to optimize a security algorithm designwith RDI in terms of area, speed and power. The authors also showed that RDI is an efficientcountermeasure technique on FPGA in comparison to other countermeasures.In this article, a new RDI logic design is proposed that can be used to cost-efficiently implementRDI on FPGA devices. Sliding-Window DPA and realignment attacks, which were shown to beeffective against RDI implemented on smartcard devices, are performed on the improved RDIFPGA implementation. We demonstrate that these attacks are unsuccessful and we also proposea realignment technique that can be used to demonstrate the weakness of RDI implementations.

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.

Real-valued fixed-complexity sphere decoder for high dimensional QAM-MIMO systems

The development of high performance, low computational complexity detection algorithms is a key challenge for real-time Multiple-Input Multiple-Output (MIMO) communication system design. The Fixed-Complexity Sphere Decoder (FSD) algorithm is one of the most promising approaches, enabling quasi-ML decoding accuracy and high performance implementation due to its deterministic, highly parallel structure. However, it suffers from exponential growth in computational complexity as the number of MIMO transmit antennas increases, critically limiting its scalability to larger MIMO system topologies. In this paper, we present a solution to this problem by applying a novel cutting protocol to the decoding tree of a real-valued FSD algorithm. The new Real-valued Fixed-Complexity Sphere Decoder (RFSD) algorithm derived achieves similar quasi-ML decoding performance as FSD, but with an average 70% reduction in computational complexity, as we demonstrate from both theoretical and implementation perspectives for Quadrature Amplitude Modulation (QAM)-MIMO systems.

John P. Mackintosh, Devolution and the Union

This article provides a discussion of the political thinking of John P. Mackintosh (1929–1978) around the debate over Scottish devolution, and the constitutional reform of the UK, during the 1960s and 1970s. The article explores Mackintosh's ‘Union State’ vision of the UK and connects this to his interest in, and study of, the Northern Ireland experience of devolution from 1921 to 1972. It also considers the significance of Mackintosh's confrontations with Scottish nationalism and suggests that his unionism was representative of a more authentic and rooted tradition than is usually acknowledged. The article offers an evaluation of Mackintosh's legacy and considers the extent to which the questions he posed, and the lines of argument he advanced, have retained their relevance and interest in the new context of partial devolution in the UK, and in the current period of renewed constitutional speculation and debate over the future of the Union and the UK.