Derivation of Change from Sequences of Snapshots

Current research in the domain of geographic information science considers possibilities of including another dimension, time, which is generally missing to this point. Users interested in changes have few functions available to compare datasets of spatial configurations at different points in time. Such a comparison of spatial configurations requires large amounts of manual labor. An automatic derivation of changes would decrease amounts of manual labor. The thesis introduces a set of methods that allows for an automatic derivation of changes. These methods analyze identity and topological states of objects in snapshots and derive types of change for the specific configuration of data. The set of change types that can be computed by the methods presented includes continuous changes such as growing, shrinking, and moving of objects. For these continuous changes identity remains unchanged, while topological relations might be altered over time. Also discrete changes such as merging and splitting where both identity and topology are affected can be derived. Evaluation of the methods using a prototype application with simple examples suggests that the methods compute uniquely and correctly the type of change that applied in spatial scenarios captured in two snapshots.

Pollen analysis of modern mangrove systems

Three sediment cores from the Bragança Peninsula located in the coastal region in the north-eastern portion of Pará State have been studied by pollen analysis to reconstruct Holocene environmental changes and dynamics of the mangrove ecosystem. The cores were taken from an Avicennia forest (Bosque de Avicennia (BDA)), a salt marsh area (Campo Salgado (CS)) and a Rhizophora dominated area (Furo do Chato). Pollen traps were installed in five different areas of the peninsula to study modern pollen deposition. Nine accelerator mass spectrometry radiocarbon dates provide time control and show that sediment deposits accumulated relatively undisturbed. Mangrove vegetation started to develop at different times at the three sites: at 5120 14C yr BP at the CS site, at 2170 14C yr BP at the BDA site and at 1440 14C yr BP at the FDC site. Since mid Holocene times, the mangroves covered even the most elevated area on the peninsula, which is today a salt marsh, suggesting somewhat higher relative sea-levels. The pollen concentration in relatively undisturbed deposits seems to be an indicator for the frequency of inundation. The tidal inundation frequency decreased, probably related to lower sea-levels, during the late Holocene around 1770 14C yr BP at BDA, around 910 14C yr BP at FDC and around 750 14C yr BP at CS. The change from a mangrove ecosystem to a salt marsh on the higher elevation, around 420 14C yr BP is probably natural and not due to an anthropogenic impact. Modern pollen rain from different mangrove types show different ratios between Rhizophora and Avicennia pollen, which can be used to reconstruct past composition of the mangrove. In spite of bioturbation and especially tidal inundation, which change the local pollen deposition within the mangrove zone, past mangrove dynamics can be reconstructed. The pollen record for BDA indicates a mixed Rhizophora/Avicennia mangrove vegetation between 2170 and 1770 14C yr BP. Later Rhizophora trees became more frequent and since ca. 200 14C yr BP Avicennia dominated in the forest.

Preconditioning in the reef-building coral Pocillopora damicornis and the potential for trans-generational acclimatization in coral larvae under future climate change conditions

Coral reefs are globally threatened by climate change-related ocean warming and ocean acidification (OA). To date, slow-response mechanisms such as genetic adaptation have been considered the major determinant of coral reef persistence, with little consideration of rapid-response acclimatization mechanisms. These rapid mechanisms such as parental effects that can contribute to trans-generational acclimatization (e.g. epigenetics) have, however, been identified as important contributors to offspring response in other systems. We present the first evidence of parental effects in a cross-generational exposure to temperature and OA in reef-building corals. Here, we exposed adults to high (28.9°C, 805 µatm PCO2) or ambient (26.5°C, 417 µatm PCO2) temperature and OA treatments during the larval brooding period. Exposure to high treatment negatively affected adult performance, but their larvae exhibited size differences and metabolic acclimation when subsequently re-exposed, unlike larvae from parents exposed to ambient conditions. Understanding the innate capacity corals possess to respond to current and future climatic conditions is essential to reef protection and maintenance. Our results identify that parental effects may have an important role through (1) ameliorating the effects of stress through preconditioning and adaptive plasticity, and/or (2) amplifying the negative parental response through latent effects on future life stages. Whether the consequences of parental effects and the potential for trans-generational acclimatization are beneficial or maladaptive, our work identifies a critical need to expand currently proposed climate change outcomes for corals to further assess rapid response mechanisms that include non-genetic inheritance through parental contributions and classical epigenetic mechanisms.

Coastal Urban Flood Resislience versus Climate Change

Processes of founding and expanding cities in coastal areas have undergone great changes over time driven by environmental conditions. Coastal settlements looked for places above flood levels and away from swamps and other wetlands whenever possible. As populations grew, cities were extending trying to avoid low and wet lands. No city has been able to limit its growth. The risk of flooding can never be eliminated, but only reduced to the extent possible. Flooding of coastal areas is today dramatically attributed to eustasic sea level rise caused by global climate change. This can be inaccurate. Current climate change is generating an average sea level upward trend, but other regional and local factors result in this trend being accentuated in some places or attenuated, and even reversed, in others. Then, the intensity and frequency of coastal flooding around the planet, although not so much as a unique result of this general eustasic elevation, but rather of the superposition of marine and crustal dynamic elements, the former also climate-related, which give rise to a temporary raising in average sea level in the short term. Since the Little Ice Age the planet has been suffering a global warming change leading to sea level rise. The idea of being too obeying to anthropogenic factors may be attributed to Arrhenius (1896), though it is of much later highlight after the sixties of the last century. Never before, the human factor had been able of such an influence on climate. However, other types of changes in sea levels became apparent, resulting from vertical movements of the crust, modifications of sea basins due to continents fracturing, drifting and coming together, or to different types of climate patterns. Coastal zones are then doubly susceptible to floods. Precipitation immediately triggers pluvial flooding. If it continues upland or when snow and glaciers melt eventually fluvial flooding can occur. The urban development presence represents modifying factors. Additional interference is caused by river and waste water drainage systems. Climate also influences sea levels in coastal areas, where tides as well as the structure and dynamic of the geoid and its crust come into play. From the sea, waters can flood and break or push back berms and other coastline borders. The sea level, controlling the mouth of the main channel of the basin's drainage system, is ultimately what governs flood levels. A temporary rise in sea level acts as a dam at the mouth. Even in absence of that global change, so, floods are likely going to increase in many urban coastal areas. Some kind of innovative methodologies and practices should be needed to get more flood resilience cities

Response timing in the lunge and target change in elite versus medium-level fencers.

The aim of the present work is to examine the differences between two groups of fencers with different levels of competition, elite and medium level. The timing parameters of the response reaction have been compared together with the kinetic variables which determine the sequence of segmented participation used during the lunge with a change in target during movement. A total of 30 male sword fencers participated, 13 elite and 17 medium level. Two force platforms recorded the horizontal component of the force and the start of the movement. One system filmed the movement in 3D, recording the spatial positions of 11 markers, while another system projected a mobile target over a screen. For synchronisation, an electronic signal enabled all the systems to be started simultaneously. Among the timing parameters of the reaction response, the choice reaction time (CRT) to the target change during the lunge was measured. The results revealed differences between the groups regarding the flight time, horizontal velocity at the end of the acceleration phase, and the length of the lunge, these being higher for the elite group, as well as other variables related to the temporal sequence of movement. No significant differences have been found in the simple reaction time or in CRT. According to the literature, the CRT appears to improve with sports practice, although this factor did not differentiate the elite from medium-level fencers. The coordination of fencing movements, that is, the right technique, constitutes a factor that differentiates elite fencers from medium-level ones.

Impacts of projected maximum temperature extremes for C21 by an ensemble of regional climate models on cereal cropping systems in the Iberian Peninsula

Crops growing in the Iberian Peninsula may be subjected to damagingly high temperatures during the sensitive development periods of flowering and grain filling. Such episodes are considered important hazards and farmers may take insurance to offset their impact. Increases in value and frequency of maximum temperature have been observed in the Iberian Peninsula during the 20th century, and studies on climate change indicate the possibility of further increase by the end of the 21st century. Here, impacts of current and future high temperatures on cereal cropping systems of the Iberian Peninsula are evaluated, focusing on vulnerable development periods of winter and summer crops. Climate change scenarios obtained from an ensemble of ten Regional Climate Models (multimodel ensemble) combined with crop simulation models were used for this purpose and related uncertainty was estimated. Results reveal that higher extremes of maximum temperature represent a threat to summer-grown but not to winter-grown crops in the Iberian Peninsula. The study highlights the different vulnerability of crops in the two growing seasons and the need to account for changes in extreme temperatures in developing adaptations in cereal cropping systems. Finally, this work contributes to clarifying the causes of high-uncertainty impact projections from previous studies.

Climate Change Impacts on Maize and Dry Bean Yields of smallholder farmers in Honduras

The rotation maize and dry bean provides the main food supply of smallholder farmers in Honduras. Crop model assessment of climate change impacts (2070?2099 compared to a 1961?1990 baseline) on a maize?dry bean rotation for several sites across a range of climatic zones and elevations in Honduras. Low productivity systems, together with an uncertain future climate, pose a high level of risk for food security. The cropping systems simulation dynamic model CropSyst was calibrated and validated upon field trail site at Zamorano, then run with baseline and future climate scenarios based upon general circulation models (GCM) and the ClimGen synthetic daily weather generator. Results indicate large uncertainty in crop production from various GCM simulations and future emissions scenarios, but generally reduced yields at low elevations by 0 % to 22 % in suitable areas for crop production and increased yield at the cooler, on the hillsides, where farming needs to reduce soil erosion with conservation techniques. Further studies are needed to investigate strategies to reduce impacts and to explore adaptation tactics.

Idea relationship analysis in open innovation crowdsourcing systems

Idea Management Systems are an implementation of open innovation notion in the Web environment with the use of crowdsourcing techniques. In this area, one of the popular methods for coping with large amounts of data is duplicate de- tection. With our research, we answer a question if there is room to introduce more relationship types and in what degree would this change affect the amount of idea metadata and its diversity. Furthermore, based on hierarchical dependencies between idea relationships and relationship transitivity we propose a number of methods for dataset summarization. To evaluate our hypotheses we annotate idea datasets with new relationships using the contemporary methods of Idea Management Systems to detect idea similarity. Having datasets with relationship annotations at our disposal, we determine if idea features not related to idea topic (e.g. innovation size) have any relation to how annotators perceive types of idea similarity or dissimilarity.

Real time passenger information systems and quality of bus services

One of the main problems in urban areas is the steady growth in car ownership and traffic levels. Therefore, the challenge of sustainability is focused on a shift of the demand for mobility from cars to collective means of transport. For this end, buses are a key element of the public transport systems. In this respect Real Time Passenger Information (RTPI) systems help citizens change their travel behaviour towards more sustainable transport modes. This paper provides an assessment methodology which evaluates how RTPI systems improve the quality of bus services in two European cities, Madrid and Bremerhaven. In the case of Madrid, bus punctuality has increased by 3%. Regarding the travellers perception, Madrid raised its quality of service by 6% while Bremerhaven increased by 13%. On the other hand, the users ́ perception of Public Transport (PT) image increased by 14%.

Water scarcity and climate change impact and vulnerability in irrigated agriculture in Mediterranean river basins

Actualmente, la escasez de agua constituye un importante problema en muchos lugares del mundo. El crecimiento de la población, la creciente necesidad de alimentos, el desarrollo socio-económico y el cambio climático ejercen una importante y cada vez mayor presión sobre los recursos hídricos, a la que muchos países van a tener que enfrentarse en los próximos anos. La región Mediterránea es una de las regiones del mundo de mayor escasez de recursos hídricos, y es además una de las zonas más vulnerables al cambio climático. La mayoría de estudios sobre cambio climático prevén mayores temperaturas y una disminución de las precipitaciones, y una creciente escasez de agua debida a la disminución de recursos disponibles y al aumento de las demandas de riego. En el contexto actual de desarrollo de políticas se demanda cada vez más una mayor consideración del cambio climático en el marco de las políticas sectoriales. Sin embargo, los estudios enfocados a un solo sector no reflejan las múltiples dimensiones del los efectos del cambio climático. Numerosos estudios científicos han demostrado que el cambio climático es un fenómeno de naturaleza multi-dimensional y cuyos efectos se transmiten a múltiples escalas. Por tanto, es necesaria la producción de estudios y herramientas de análisis capaces de reflejar todas estas dimensiones y que contribuyan a la elaboración de políticas robustas en un contexto de cambio climático. Esta investigación pretende aportar una visión global de la problemática de la escasez de agua y los impactos, la vulnerabilidad y la adaptación al cambio climático en el contexto de la región mediterránea. La investigación presenta un marco integrado de modelización que se va ampliando progresivamente en un proceso secuencial y multi-escalar en el que en cada etapa se incorpora una nueva dimensión. La investigación consta de cuatro etapas que se abordan a lo largo de cuatro capítulos. En primer lugar, se estudia la vulnerabilidad económica de las explotaciones de regadío del Medio Guadiana, en España. Para ello, se utiliza un modelo de programación matemática en combinación con un modelo econométrico. A continuación, en la segunda etapa, se utiliza un modelo hidro-económico que incluye un modelo de cultivo para analizar los procesos que tienen lugar a escala de cultivo, explotación y cuenca teniendo en cuenta distintas escalas geográficas y de toma de decisiones. Esta herramienta permite el análisis de escenarios de cambio climático y la evaluación de posibles medidas de adaptación. La tercera fase consiste en el análisis de las barreras que dificultan la aplicación de procesos de adaptación para lo cual se analizan las redes socio-institucionales en la cuenca. Finalmente, la cuarta etapa aporta una visión sobre la escasez de agua y el cambio climático a escala nacional y regional mediante el estudio de distintos escenarios de futuro plausibles y los posibles efectos de las políticas en la escasez de agua. Para este análisis se utiliza un modelo econométrico de datos de panel para la región mediterránea y un modelo hidro-económico que se aplica a los casos de estudio de España y Jordania. Los resultados del estudio ponen de relieve la importancia de considerar múltiples escalas y múltiples dimensiones en el estudio de la gestión de los recursos hídricos y la adaptación al cambio climático en los contextos mediterráneos de escasez de agua estudiados. Los resultados muestran que los impactos del cambio climático en la cuenca del Guadiana y en el conjunto de España pueden comprometer la sostenibilidad del regadío y de los ecosistemas. El análisis a escala de cuenca hidrográfica resalta la importancia de las interacciones entre los distintos usuarios del agua y en concreto entre distintas comunidades de regantes, así como la necesidad de fortalecer el papel de las instituciones y de fomentar la creación de una visión común en la cuenca para facilitar la aplicación de los procesos de adaptación. Asimismo, los resultados de este trabajo evidencian también la capacidad y el papel fundamental de las políticas para lograr un desarrollo sostenible y la adaptación al cambio climático es regiones de escasez de agua tales como la región mediterránea. Especialmente, este trabajo pone de manifiesto el potencial de la Directiva Marco del Agua de la Unión Europea para lograr una efectiva adaptación al cambio climático. Sin embargo, en Jordania, además de la adaptación al cambio climático, es preciso diseñar estrategias de desarrollo sostenible más ambiciosas que contribuyan a reducir el riesgo futuro de escasez de agua. ABSTRACT Water scarcity is becoming a major concern in many parts of the world. Population growth, increasing needs for food production, socio-economic development and climate change represent pressures on water resources that many countries around the world will have to deal in the coming years. The Mediterranean region is one of the most water scarce regions of the world and is considered a climate change hotspot. Most projections of climate change envisage an increase in temperatures and a decrease in precipitation and a resulting reduction in water resources availability as a consequence of both reduced water availability and increased irrigation demands. Current policy development processes require the integration of climate change concerns into sectoral policies. However, sector-oriented studies often fail to address all the dimensions of climate change implications. Climate change research in the last years has evidenced the need for more integrated studies and methodologies that are capable of addressing the multi-scale and multi-dimensional nature of climate change. This research attempts to provide a comprehensive view of water scarcity and climate change impacts, vulnerability and adaptation in Mediterranean contexts. It presents an integrated modelling framework that is progressively enlarged in a sequential multi-scale process in which a new dimension of climate change and water resources is addressed at every stage. It is comprised of four stages, each one explained in a different chapter. The first stage explores farm-level economic vulnerability in the Spanish Guadiana basin using a mathematical programming model in combination with an econometric model. Then, in a second stage, the use of a hydro-economic modelling framework that includes a crop growth model allows for the analysis of crop, farm and basin level processes taking into account different geographical and decision-making scales. This integrated tool is used for the analysis of climate change scenarios and for the assessment of potential adaptation options. The third stage includes the analysis of barriers to the effective implementation of adaptation processes based on socioinstitutional network analysis. Finally, a regional and country level perspective of water scarcity and climate change is provided focusing on different possible socio-economic development pathways and the effect of policies on future water scarcity. For this analysis, a panel-data econometric model and a hydro-economic model are applied for the analysis of the Mediterranean region and country level case studies in Spain and Jordan. The overall results of the study demonstrate the value of considering multiple scales and multiple dimensions in water management and climate change adaptation in the Mediterranean water scarce contexts analysed. Results show that climate change impacts in the Guadiana basin and in Spain may compromise the sustainability of irrigation systems and ecosystems. The analysis at the basin level highlights the prominent role of interactions between different water users and irrigation districts and the need to strengthen institutional capacity and common understanding in the basin to enhance the implementation of adaptation processes. The results of this research also illustrate the relevance of water policies in achieving sustainable development and climate change adaptation in water scarce areas such as the Mediterranean region. Specifically, the EU Water Framework Directive emerges as a powerful trigger for climate change adaptation. However, in Jordan, outreaching sustainable development strategies are required in addition to climate change adaptation to reduce future risk of water scarcity.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

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